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Commit c346a54a authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/host-designware' into pci/host-imx6 

* pci/host-designware:
  PCI: designware: Remove pci_assign_unassigned_resources() from dw_pcie_host_init()
  PCI: designware: Use pci_create_root_bus() instead of pci_scan_root_bus()
  PCI: designware: Parse bus-range property from devicetree
  PCI: designware: Add support for v3.65 hardware
parents 3e3e406e 8ddebc41

Documentation/devicetree/bindings/pci/designware-pcie.txt

+3 −0
Original line number Diff line number Diff line
@@ -23,3 +23,6 @@ Required properties: 


Optional properties:

- reset-gpio: gpio pin number of power good signal

- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to

  specify this property, to keep backwards compatibility a range of 0x00-0xff

  is assumed if not present)

drivers/pci/host/pcie-designware.c

+52 −27
Original line number Diff line number Diff line
@@ -425,7 +425,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp) 
	struct resource *cfg_res;

	u32 val, na, ns;

	const __be32 *addrp;

	int i, index;

	int i, index, ret;



	/* Find the address cell size and the number of cells in order to get

	 * the untranslated address.
@@ -500,6 +500,16 @@ int __init dw_pcie_host_init(struct pcie_port *pp) 
		}

	}



	ret = of_pci_parse_bus_range(np, &pp->busn);

	if (ret < 0) {

		pp->busn.name = np->name;

		pp->busn.start = 0;

		pp->busn.end = 0xff;

		pp->busn.flags = IORESOURCE_BUS;

		dev_dbg(pp->dev, "failed to parse bus-range property: %d, using default %pR\n",

			ret, &pp->busn);

	}



	if (!pp->dbi_base) {

		pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,

					resource_size(&pp->cfg));
@@ -511,18 +521,25 @@ int __init dw_pcie_host_init(struct pcie_port *pp) 


	pp->mem_base = pp->mem.start;



	if (!pp->va_cfg0_base) {

		pp->cfg0_base = pp->cfg.start;

		pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,

						pp->config.cfg0_size);

		if (!pp->va_cfg0_base) {

			dev_err(pp->dev, "error with ioremap in function\n");

			return -ENOMEM;

		}

	}



	if (!pp->va_cfg1_base) {

		pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;

		pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,

						pp->config.cfg1_size);

		if (!pp->va_cfg1_base) {

			dev_err(pp->dev, "error with ioremap\n");

			return -ENOMEM;

		}

	}



	if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {

		dev_err(pp->dev, "Failed to parse the number of lanes\n");
@@ -530,6 +547,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp) 
	}



	if (IS_ENABLED(CONFIG_PCI_MSI)) {

		if (!pp->ops->msi_host_init) {

			pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,

						MAX_MSI_IRQS, &msi_domain_ops,

						&dw_pcie_msi_chip);
@@ -540,6 +558,11 @@ int __init dw_pcie_host_init(struct pcie_port *pp) 


			for (i = 0; i < MAX_MSI_IRQS; i++)

				irq_create_mapping(pp->irq_domain, i);

		} else {

			ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);

			if (ret < 0)

				return ret;

		}

	}



	if (pp->ops->host_init)
@@ -558,7 +581,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp) 
	dw_pci.private_data = (void **)&pp;



	pci_common_init_dev(pp->dev, &dw_pci);

	pci_assign_unassigned_resources();

#ifdef CONFIG_PCI_DOMAINS

	dw_pci.domain++;

#endif
@@ -781,6 +803,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys) 


	sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr;

	pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);

	pci_add_resource(&sys->resources, &pp->busn);



	return 1;

}
@@ -790,14 +813,16 @@ static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) 
	struct pci_bus *bus;

	struct pcie_port *pp = sys_to_pcie(sys);



	if (pp) {

	pp->root_bus_nr = sys->busnr;

		bus = pci_scan_root_bus(pp->dev, sys->busnr, &dw_pcie_ops,

					sys, &sys->resources);

	} else {

		bus = NULL;

		BUG();

	}

	bus = pci_create_root_bus(pp->dev, sys->busnr,

				  &dw_pcie_ops, sys, &sys->resources);

	if (!bus)

		return NULL;



	pci_scan_child_bus(bus);



	if (bus && pp->ops->scan_bus)

		pp->ops->scan_bus(pp);



	return bus;

}

drivers/pci/host/pcie-designware.h

+3 −0
Original line number Diff line number Diff line
@@ -48,6 +48,7 @@ struct pcie_port { 
	struct resource		cfg;

	struct resource		io;

	struct resource		mem;

	struct resource		busn;

	struct pcie_port_info	config;

	int			irq;

	u32			lanes;
@@ -74,6 +75,8 @@ struct pcie_host_ops { 
	void (*msi_set_irq)(struct pcie_port *pp, int irq);

	void (*msi_clear_irq)(struct pcie_port *pp, int irq);

	u32 (*get_msi_data)(struct pcie_port *pp);

	void (*scan_bus)(struct pcie_port *pp);

	int (*msi_host_init)(struct pcie_port *pp, struct msi_chip *chip);

};



int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);