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Commit c3307cd6 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-radeon-ni' of ../drm-radeon-next into drm-core-next 

* 'drm-radeon-ni' of ../drm-radeon-next: (30 commits)
  radeon: consolidate asic-specific function decls for pre-r600
  drm/radeon/kms: add NI pci ids
  drm/radeon/kms: don't enable pcie gen2 on NI yet
  drm/radeon/kms: add radeon_asic struct for NI asics
  drm/radeon/kms/ni: load default sclk/mclk/vddc at pm init
  drm/radeon/kms: add ucode loader for NI
  drm/radeon/kms: add support for DCE5 display LUTs
  drm/radeon/kms: add ni_reg.h
  drm/radeon/kms: add bo blit support for NI
  drm/radeon/kms: always use writeback/events for fences on NI
  drm/radeon/kms: adjust default clock/vddc tracking for pm on DCE5
  drm/radeon/kms: add backend map workaround for barts
  drm/radeon/kms: fill gpu init for NI asics
  drm/radeon/kms: add disabled vbios accessor for NI asics
  drm/radeon/kms: handle NI thermal controller
  drm/radeon/kms: parse DCE5 encoder caps when setting up encoders
  drm/radeon/kms: dvo dpms updates for DCE5
  drm/radeon/kms: dac dpms updates for DCE5
  drm/radeon/kms: DCE5 atom dig encoder updates
  drm/radeon/kms: DCE5 atom transmitter control updates
  ...
parents 0ba41e44 187f3da3

drivers/gpu/drm/radeon/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -66,7 +66,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ 
	r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \

	r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \

	evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \

	radeon_trace_points.o

	radeon_trace_points.o ni.o



radeon-$(CONFIG_COMPAT) += radeon_ioc32.o

radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o

drivers/gpu/drm/radeon/atombios_crtc.c

+53 −4
Original line number Diff line number Diff line
@@ -403,6 +403,7 @@ union atom_enable_ss { 
	ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;

	ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;

	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;

	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;

};



static void atombios_crtc_program_ss(struct drm_crtc *crtc,
@@ -417,7 +418,30 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc, 


	memset(&args, 0, sizeof(args));



	if (ASIC_IS_DCE4(rdev)) {

	if (ASIC_IS_DCE5(rdev)) {

		args.v3.usSpreadSpectrumAmountFrac = 0;

		args.v3.ucSpreadSpectrumType = ss->type;

		switch (pll_id) {

		case ATOM_PPLL1:

			args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;

			args.v3.usSpreadSpectrumAmount = ss->amount;

			args.v3.usSpreadSpectrumStep = ss->step;

			break;

		case ATOM_PPLL2:

			args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;

			args.v3.usSpreadSpectrumAmount = ss->amount;

			args.v3.usSpreadSpectrumStep = ss->step;

			break;

		case ATOM_DCPLL:

			args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;

			args.v3.usSpreadSpectrumAmount = 0;

			args.v3.usSpreadSpectrumStep = 0;

			break;

		case ATOM_PPLL_INVALID:

			return;

		}

		args.v2.ucEnable = enable;

	} else if (ASIC_IS_DCE4(rdev)) {

		args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);

		args.v2.ucSpreadSpectrumType = ss->type;

		switch (pll_id) {
@@ -673,9 +697,14 @@ union set_pixel_clock { 
	PIXEL_CLOCK_PARAMETERS_V2 v2;

	PIXEL_CLOCK_PARAMETERS_V3 v3;

	PIXEL_CLOCK_PARAMETERS_V5 v5;

	PIXEL_CLOCK_PARAMETERS_V6 v6;

};



static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)

/* on DCE5, make sure the voltage is high enough to support the

 * required disp clk.

 */

static void atombios_crtc_set_dcpll(struct drm_crtc *crtc,

				    u32 dispclk)

{

	struct drm_device *dev = crtc->dev;

	struct radeon_device *rdev = dev->dev_private;
@@ -698,9 +727,16 @@ static void atombios_crtc_set_dcpll(struct drm_crtc *crtc) 
			 * SetPixelClock provides the dividers

			 */

			args.v5.ucCRTC = ATOM_CRTC_INVALID;

			args.v5.usPixelClock = rdev->clock.default_dispclk;

			args.v5.usPixelClock = dispclk;

			args.v5.ucPpll = ATOM_DCPLL;

			break;

		case 6:

			/* if the default dcpll clock is specified,

			 * SetPixelClock provides the dividers

			 */

			args.v6.ulDispEngClkFreq = dispclk;

			args.v6.ucPpll = ATOM_DCPLL;

			break;

		default:

			DRM_ERROR("Unknown table version %d %d\n", frev, crev);

			return;
@@ -784,6 +820,18 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc, 
			args.v5.ucEncoderMode = encoder_mode;

			args.v5.ucPpll = pll_id;

			break;

		case 6:

			args.v6.ulCrtcPclkFreq.ucCRTC = crtc_id;

			args.v6.ulCrtcPclkFreq.ulPixelClock = cpu_to_le32(clock / 10);

			args.v6.ucRefDiv = ref_div;

			args.v6.usFbDiv = cpu_to_le16(fb_div);

			args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);

			args.v6.ucPostDiv = post_div;

			args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */

			args.v6.ucTransmitterID = encoder_id;

			args.v6.ucEncoderMode = encoder_mode;

			args.v6.ucPpll = pll_id;

			break;

		default:

			DRM_ERROR("Unknown table version %d %d\n", frev, crev);

			return;
@@ -1377,7 +1425,8 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc, 
								   rdev->clock.default_dispclk);

		if (ss_enabled)

			atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss);

		atombios_crtc_set_dcpll(crtc);

		/* XXX: DCE5, make sure voltage, dispclk is high enough */

		atombios_crtc_set_dcpll(crtc, rdev->clock.default_dispclk);

		if (ss_enabled)

			atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss);

	}

drivers/gpu/drm/radeon/evergreen.c

+161 −8
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ 


static void evergreen_gpu_init(struct radeon_device *rdev);

void evergreen_fini(struct radeon_device *rdev);

static void evergreen_pcie_gen2_enable(struct radeon_device *rdev);



void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)

{
@@ -400,15 +401,27 @@ static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev, 
	case 0:

	case 4:

	default:

		if (ASIC_IS_DCE5(rdev))

			return 4096 * 2;

		else

			return 3840 * 2;

	case 1:

	case 5:

		if (ASIC_IS_DCE5(rdev))

			return 6144 * 2;

		else

			return 5760 * 2;

	case 2:

	case 6:

		if (ASIC_IS_DCE5(rdev))

			return 8192 * 2;

		else

			return 7680 * 2;

	case 3:

	case 7:

		if (ASIC_IS_DCE5(rdev))

			return 2048 * 2;

		else

			return 1920 * 2;

	}

}
@@ -1146,7 +1159,7 @@ static void evergreen_mc_program(struct radeon_device *rdev) 
	tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);

	WREG32(MC_VM_FB_LOCATION, tmp);

	WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));

	WREG32(HDP_NONSURFACE_INFO, (2 << 7));

	WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));

	WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);

	if (rdev->flags & RADEON_IS_AGP) {

		WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
@@ -1371,11 +1384,14 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev, 
	case CHIP_CEDAR:

	case CHIP_REDWOOD:

	case CHIP_PALM:

	case CHIP_TURKS:

	case CHIP_CAICOS:

		force_no_swizzle = false;

		break;

	case CHIP_CYPRESS:

	case CHIP_HEMLOCK:

	case CHIP_JUNIPER:

	case CHIP_BARTS:

	default:

		force_no_swizzle = true;

		break;
@@ -1489,6 +1505,7 @@ static void evergreen_program_channel_remap(struct radeon_device *rdev) 
	switch (rdev->family) {

	case CHIP_HEMLOCK:

	case CHIP_CYPRESS:

	case CHIP_BARTS:

		tcp_chan_steer_lo = 0x54763210;

		tcp_chan_steer_hi = 0x0000ba98;

		break;
@@ -1496,6 +1513,8 @@ static void evergreen_program_channel_remap(struct radeon_device *rdev) 
	case CHIP_REDWOOD:

	case CHIP_CEDAR:

	case CHIP_PALM:

	case CHIP_TURKS:

	case CHIP_CAICOS:

	default:

		tcp_chan_steer_lo = 0x76543210;

		tcp_chan_steer_hi = 0x0000ba98;
@@ -1635,6 +1654,69 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
		rdev->config.evergreen.max_hw_contexts = 4;

		rdev->config.evergreen.sq_num_cf_insts = 1;



		rdev->config.evergreen.sc_prim_fifo_size = 0x40;

		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

		break;

	case CHIP_BARTS:

		rdev->config.evergreen.num_ses = 2;

		rdev->config.evergreen.max_pipes = 4;

		rdev->config.evergreen.max_tile_pipes = 8;

		rdev->config.evergreen.max_simds = 7;

		rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;

		rdev->config.evergreen.max_gprs = 256;

		rdev->config.evergreen.max_threads = 248;

		rdev->config.evergreen.max_gs_threads = 32;

		rdev->config.evergreen.max_stack_entries = 512;

		rdev->config.evergreen.sx_num_of_sets = 4;

		rdev->config.evergreen.sx_max_export_size = 256;

		rdev->config.evergreen.sx_max_export_pos_size = 64;

		rdev->config.evergreen.sx_max_export_smx_size = 192;

		rdev->config.evergreen.max_hw_contexts = 8;

		rdev->config.evergreen.sq_num_cf_insts = 2;



		rdev->config.evergreen.sc_prim_fifo_size = 0x100;

		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

		break;

	case CHIP_TURKS:

		rdev->config.evergreen.num_ses = 1;

		rdev->config.evergreen.max_pipes = 4;

		rdev->config.evergreen.max_tile_pipes = 4;

		rdev->config.evergreen.max_simds = 6;

		rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;

		rdev->config.evergreen.max_gprs = 256;

		rdev->config.evergreen.max_threads = 248;

		rdev->config.evergreen.max_gs_threads = 32;

		rdev->config.evergreen.max_stack_entries = 256;

		rdev->config.evergreen.sx_num_of_sets = 4;

		rdev->config.evergreen.sx_max_export_size = 256;

		rdev->config.evergreen.sx_max_export_pos_size = 64;

		rdev->config.evergreen.sx_max_export_smx_size = 192;

		rdev->config.evergreen.max_hw_contexts = 8;

		rdev->config.evergreen.sq_num_cf_insts = 2;



		rdev->config.evergreen.sc_prim_fifo_size = 0x100;

		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

		break;

	case CHIP_CAICOS:

		rdev->config.evergreen.num_ses = 1;

		rdev->config.evergreen.max_pipes = 4;

		rdev->config.evergreen.max_tile_pipes = 2;

		rdev->config.evergreen.max_simds = 2;

		rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;

		rdev->config.evergreen.max_gprs = 256;

		rdev->config.evergreen.max_threads = 192;

		rdev->config.evergreen.max_gs_threads = 16;

		rdev->config.evergreen.max_stack_entries = 256;

		rdev->config.evergreen.sx_num_of_sets = 4;

		rdev->config.evergreen.sx_max_export_size = 128;

		rdev->config.evergreen.sx_max_export_pos_size = 32;

		rdev->config.evergreen.sx_max_export_smx_size = 96;

		rdev->config.evergreen.max_hw_contexts = 4;

		rdev->config.evergreen.sq_num_cf_insts = 1;



		rdev->config.evergreen.sc_prim_fifo_size = 0x40;

		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
@@ -1780,6 +1862,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
		switch (rdev->family) {

		case CHIP_CYPRESS:

		case CHIP_HEMLOCK:

		case CHIP_BARTS:

			gb_backend_map = 0x66442200;

			break;

		case CHIP_JUNIPER:
@@ -1918,6 +2001,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
	switch (rdev->family) {

	case CHIP_CEDAR:

	case CHIP_PALM:

	case CHIP_CAICOS:

		/* no vertex cache */

		sq_config &= ~VC_ENABLE;

		break;
@@ -1977,6 +2061,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
	switch (rdev->family) {

	case CHIP_CEDAR:

	case CHIP_PALM:

	case CHIP_CAICOS:

		vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);

		break;

	default:
@@ -2767,6 +2852,24 @@ static int evergreen_startup(struct radeon_device *rdev) 
{

	int r;



	/* enable pcie gen2 link */

	if (!ASIC_IS_DCE5(rdev))

		evergreen_pcie_gen2_enable(rdev);



	if (ASIC_IS_DCE5(rdev)) {

		if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {

			r = ni_init_microcode(rdev);

			if (r) {

				DRM_ERROR("Failed to load firmware!\n");

				return r;

			}

		}

		r = btc_mc_load_microcode(rdev);

		if (r) {

			DRM_ERROR("Failed to load MC firmware!\n");

			return r;

		}

	} else {

		if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {

			r = r600_init_microcode(rdev);

			if (r) {
@@ -2774,6 +2877,7 @@ static int evergreen_startup(struct radeon_device *rdev) 
				return r;

			}

		}

	}



	evergreen_mc_program(rdev);

	if (rdev->flags & RADEON_IS_AGP) {
@@ -3049,3 +3153,52 @@ void evergreen_fini(struct radeon_device *rdev) 
	rdev->bios = NULL;

	radeon_dummy_page_fini(rdev);

}



static void evergreen_pcie_gen2_enable(struct radeon_device *rdev)

{

	u32 link_width_cntl, speed_cntl;



	if (rdev->flags & RADEON_IS_IGP)

		return;



	if (!(rdev->flags & RADEON_IS_PCIE))

		return;



	/* x2 cards have a special sequence */

	if (ASIC_IS_X2(rdev))

		return;



	speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);

	if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||

	    (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {



		link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);

		link_width_cntl &= ~LC_UPCONFIGURE_DIS;

		WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);



		speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);

		speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;

		WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);



		speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);

		speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;

		WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);



		speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);

		speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;

		WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);



		speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);

		speed_cntl |= LC_GEN2_EN_STRAP;

		WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);



	} else {

		link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);

		/* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */

		if (1)

			link_width_cntl |= LC_UPCONFIGURE_DIS;

		else

			link_width_cntl &= ~LC_UPCONFIGURE_DIS;

		WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);

	}

}

drivers/gpu/drm/radeon/evergreen_blit_kms.c

+67 −2
Original line number Diff line number Diff line
@@ -148,7 +148,8 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) 
	radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);



	if ((rdev->family == CHIP_CEDAR) ||

	    (rdev->family == CHIP_PALM))

	    (rdev->family == CHIP_PALM) ||

	    (rdev->family == CHIP_CAICOS))

		cp_set_surface_sync(rdev,

				    PACKET3_TC_ACTION_ENA, 48, gpu_addr);

	else
@@ -353,10 +354,74 @@ set_default_state(struct radeon_device *rdev) 
		num_hs_stack_entries = 42;

		num_ls_stack_entries = 42;

		break;

	case CHIP_BARTS:

		num_ps_gprs = 93;

		num_vs_gprs = 46;

		num_temp_gprs = 4;

		num_gs_gprs = 31;

		num_es_gprs = 31;

		num_hs_gprs = 23;

		num_ls_gprs = 23;

		num_ps_threads = 128;

		num_vs_threads = 20;

		num_gs_threads = 20;

		num_es_threads = 20;

		num_hs_threads = 20;

		num_ls_threads = 20;

		num_ps_stack_entries = 85;

		num_vs_stack_entries = 85;

		num_gs_stack_entries = 85;

		num_es_stack_entries = 85;

		num_hs_stack_entries = 85;

		num_ls_stack_entries = 85;

		break;

	case CHIP_TURKS:

		num_ps_gprs = 93;

		num_vs_gprs = 46;

		num_temp_gprs = 4;

		num_gs_gprs = 31;

		num_es_gprs = 31;

		num_hs_gprs = 23;

		num_ls_gprs = 23;

		num_ps_threads = 128;

		num_vs_threads = 20;

		num_gs_threads = 20;

		num_es_threads = 20;

		num_hs_threads = 20;

		num_ls_threads = 20;

		num_ps_stack_entries = 42;

		num_vs_stack_entries = 42;

		num_gs_stack_entries = 42;

		num_es_stack_entries = 42;

		num_hs_stack_entries = 42;

		num_ls_stack_entries = 42;

		break;

	case CHIP_CAICOS:

		num_ps_gprs = 93;

		num_vs_gprs = 46;

		num_temp_gprs = 4;

		num_gs_gprs = 31;

		num_es_gprs = 31;

		num_hs_gprs = 23;

		num_ls_gprs = 23;

		num_ps_threads = 128;

		num_vs_threads = 10;

		num_gs_threads = 10;

		num_es_threads = 10;

		num_hs_threads = 10;

		num_ls_threads = 10;

		num_ps_stack_entries = 42;

		num_vs_stack_entries = 42;

		num_gs_stack_entries = 42;

		num_es_stack_entries = 42;

		num_hs_stack_entries = 42;

		num_ls_stack_entries = 42;

		break;

	}



	if ((rdev->family == CHIP_CEDAR) ||

	    (rdev->family == CHIP_PALM))

	    (rdev->family == CHIP_PALM) ||

	    (rdev->family == CHIP_CAICOS))

		sq_config = 0;

	else

		sq_config = VC_ENABLE;

drivers/gpu/drm/radeon/evergreend.h

+41 −3
Original line number Diff line number Diff line
@@ -581,6 +581,44 @@ 
#       define DC_HPDx_RX_INT_TIMER(x)                    ((x) << 16)

#       define DC_HPDx_EN                                 (1 << 28)



/* PCIE link stuff */

#define PCIE_LC_TRAINING_CNTL                             0xa1 /* PCIE_P */

#define PCIE_LC_LINK_WIDTH_CNTL                           0xa2 /* PCIE_P */

#       define LC_LINK_WIDTH_SHIFT                        0

#       define LC_LINK_WIDTH_MASK                         0x7

#       define LC_LINK_WIDTH_X0                           0

#       define LC_LINK_WIDTH_X1                           1

#       define LC_LINK_WIDTH_X2                           2

#       define LC_LINK_WIDTH_X4                           3

#       define LC_LINK_WIDTH_X8                           4

#       define LC_LINK_WIDTH_X16                          6

#       define LC_LINK_WIDTH_RD_SHIFT                     4

#       define LC_LINK_WIDTH_RD_MASK                      0x70

#       define LC_RECONFIG_ARC_MISSING_ESCAPE             (1 << 7)

#       define LC_RECONFIG_NOW                            (1 << 8)

#       define LC_RENEGOTIATION_SUPPORT                   (1 << 9)

#       define LC_RENEGOTIATE_EN                          (1 << 10)

#       define LC_SHORT_RECONFIG_EN                       (1 << 11)

#       define LC_UPCONFIGURE_SUPPORT                     (1 << 12)

#       define LC_UPCONFIGURE_DIS                         (1 << 13)

#define PCIE_LC_SPEED_CNTL                                0xa4 /* PCIE_P */

#       define LC_GEN2_EN_STRAP                           (1 << 0)

#       define LC_TARGET_LINK_SPEED_OVERRIDE_EN           (1 << 1)

#       define LC_FORCE_EN_HW_SPEED_CHANGE                (1 << 5)

#       define LC_FORCE_DIS_HW_SPEED_CHANGE               (1 << 6)

#       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK      (0x3 << 8)

#       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT     3

#       define LC_CURRENT_DATA_RATE                       (1 << 11)

#       define LC_VOLTAGE_TIMER_SEL_MASK                  (0xf << 14)

#       define LC_CLR_FAILED_SPD_CHANGE_CNT               (1 << 21)

#       define LC_OTHER_SIDE_EVER_SENT_GEN2               (1 << 23)

#       define LC_OTHER_SIDE_SUPPORTS_GEN2                (1 << 24)

#define MM_CFGREGS_CNTL                                   0x544c

#       define MM_WR_TO_CFG_EN                            (1 << 3)

#define LINK_CNTL2                                        0x88 /* F0 */

#       define TARGET_LINK_SPEED_MASK                     (0xf << 0)

#       define SELECTABLE_DEEMPHASIS                      (1 << 6)



/*

 * PM4

 */
@@ -610,7 +648,7 @@ 
#define	PACKET3_NOP					0x10

#define	PACKET3_SET_BASE				0x11

#define	PACKET3_CLEAR_STATE				0x12

#define	PACKET3_INDIRECT_BUFFER_SIZE			0x13

#define	PACKET3_INDEX_BUFFER_SIZE			0x13

#define	PACKET3_DISPATCH_DIRECT				0x15

#define	PACKET3_DISPATCH_INDIRECT			0x16

#define	PACKET3_INDIRECT_BUFFER_END			0x17
@@ -651,14 +689,14 @@ 
#              define PACKET3_CB8_DEST_BASE_ENA    (1 << 15)

#              define PACKET3_CB9_DEST_BASE_ENA    (1 << 16)

#              define PACKET3_CB10_DEST_BASE_ENA   (1 << 17)

#              define PACKET3_CB11_DEST_BASE_ENA   (1 << 17)

#              define PACKET3_CB11_DEST_BASE_ENA   (1 << 18)

#              define PACKET3_FULL_CACHE_ENA       (1 << 20)

#              define PACKET3_TC_ACTION_ENA        (1 << 23)

#              define PACKET3_VC_ACTION_ENA        (1 << 24)

#              define PACKET3_CB_ACTION_ENA        (1 << 25)

#              define PACKET3_DB_ACTION_ENA        (1 << 26)

#              define PACKET3_SH_ACTION_ENA        (1 << 27)

#              define PACKET3_SMX_ACTION_ENA       (1 << 28)

#              define PACKET3_SX_ACTION_ENA        (1 << 28)

#define	PACKET3_ME_INITIALIZE				0x44

#define		PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)

#define	PACKET3_COND_WRITE				0x45