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Commit c2fbd061 authored by Tomi Valkeinen's avatar Tomi Valkeinen
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OMAPDSS: HDMI: split PLL enable & config



At the moment we have one function, hdmi_pll_enable, which enables the
PLL and writes the PLL configuration to registers.

To make the HDMI PLL ahere to the DSS PLL API, split the hdmi_pll_enable
into two parts: hdmi_pll_enable which enables the PLL HW, and
hdmi_pll_set_config which writes the config.

Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
parent 03aafa2c
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+1 −0
Original line number Diff line number Diff line
@@ -316,6 +316,7 @@ int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp);
/* HDMI PLL funcs */
int hdmi_pll_enable(struct hdmi_pll_data *pll);
void hdmi_pll_disable(struct hdmi_pll_data *pll);
int hdmi_pll_set_config(struct hdmi_pll_data *pll);
void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin,
	unsigned long target_tmds);
+8 −2
Original line number Diff line number Diff line
@@ -196,13 +196,18 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)

	hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), p->pixelclock);

	/* config the PLL and PHY hdmi_set_pll_pwrfirst */
	r = hdmi_pll_enable(&hdmi.pll);
	if (r) {
		DSSDBG("Failed to lock PLL\n");
		DSSERR("Failed to enable PLL\n");
		goto err_pll_enable;
	}

	r = hdmi_pll_set_config(&hdmi.pll);
	if (r) {
		DSSERR("Failed to configure PLL\n");
		goto err_pll_cfg;
	}

	r = hdmi_phy_configure(&hdmi.phy, hdmi.pll.info.clkdco,
		hdmi.pll.info.clkout);
	if (r) {
@@ -241,6 +246,7 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
err_phy_cfg:
	hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
err_phy_pwr:
err_pll_cfg:
	hdmi_pll_disable(&hdmi.pll);
err_pll_enable:
	hdmi_power_off_core(dssdev);
+8 −2
Original line number Diff line number Diff line
@@ -214,13 +214,18 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
	hdmi_wp_set_irqstatus(&hdmi.wp,
			hdmi_wp_get_irqstatus(&hdmi.wp));

	/* config the PLL and PHY hdmi_set_pll_pwrfirst */
	r = hdmi_pll_enable(&hdmi.pll);
	if (r) {
		DSSDBG("Failed to lock PLL\n");
		DSSERR("Failed to enable PLL\n");
		goto err_pll_enable;
	}

	r = hdmi_pll_set_config(&hdmi.pll);
	if (r) {
		DSSERR("Failed to configure PLL\n");
		goto err_pll_cfg;
	}

	r = hdmi_phy_configure(&hdmi.phy, hdmi.pll.info.clkdco,
		hdmi.pll.info.clkout);
	if (r) {
@@ -259,6 +264,7 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
	hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
err_phy_pwr:
err_phy_cfg:
err_pll_cfg:
	hdmi_pll_disable(&hdmi.pll);
err_pll_enable:
	hdmi_power_off_core(dssdev);
+1 −5
Original line number Diff line number Diff line
@@ -103,7 +103,7 @@ void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin,
	pi->clkout = clkout;
}

static int hdmi_pll_config(struct hdmi_pll_data *pll)
int hdmi_pll_set_config(struct hdmi_pll_data *pll)
{
	u32 r;
	struct hdmi_pll_info *fmt = &pll->info;
@@ -179,10 +179,6 @@ int hdmi_pll_enable(struct hdmi_pll_data *pll)
	if (r)
		return r;

	r = hdmi_pll_config(pll);
	if (r)
		return r;

	return 0;
}