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Commit c29ecac1 authored by Daniel Jacobowitz's avatar Daniel Jacobowitz Committed by Russell King
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[ARM] 3749/3: Correct VFP single/double conversion emulation 



Patch from Daniel Jacobowitz

The fcvtsd/fcvtds emulation was left behind when the numbering of double
precision registers was changed from 0-30 to 0-15.  Both conversion
instructions were writing their results to the wrong register.  Also,
the conversion instructions should stop after the first element even
if a vector length is specified.

Signed-off-by: default avatarDaniel Jacobowitz <dan@codesourcery.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 7c6f2514

arch/arm/vfp/vfpdouble.c

+21 −7
Original line number Diff line number Diff line
@@ -1127,7 +1127,7 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr) 
{

	u32 op = inst & FOP_MASK;

	u32 exceptions = 0;

	unsigned int dd = vfp_get_dd(inst);

	unsigned int dest;

	unsigned int dn = vfp_get_dn(inst);

	unsigned int dm = vfp_get_dm(inst);

	unsigned int vecitr, veclen, vecstride;
@@ -1136,11 +1136,21 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr) 
	veclen = fpscr & FPSCR_LENGTH_MASK;

	vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK)) * 2;



	/*

	 * fcvtds takes an sN register number as destination, not dN.

	 * It also always operates on scalars.

	 */

	if ((inst & FEXT_MASK) == FEXT_FCVT) {

		veclen = 0;

		dest = vfp_get_sd(inst);

	} else

		dest = vfp_get_dd(inst);



	/*

	 * If destination bank is zero, vector length is always '1'.

	 * ARM DDI0100F C5.1.3, C5.3.2.

	 */

	if (FREG_BANK(dd) == 0)

	if (FREG_BANK(dest) == 0)

		veclen = 0;



	pr_debug("VFP: vecstride=%u veclen=%u\n", vecstride,
@@ -1153,16 +1163,20 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr) 
	for (vecitr = 0; vecitr <= veclen; vecitr += 1 << FPSCR_LENGTH_BIT) {

		u32 except;



		if (op == FOP_EXT)

		if (op == FOP_EXT && (inst & FEXT_MASK) == FEXT_FCVT)

			pr_debug("VFP: itr%d (s%u) = op[%u] (d%u)\n",

				 vecitr >> FPSCR_LENGTH_BIT,

				 dest, dn, dm);

		else if (op == FOP_EXT)

			pr_debug("VFP: itr%d (d%u) = op[%u] (d%u)\n",

				 vecitr >> FPSCR_LENGTH_BIT,

				 dd, dn, dm);

				 dest, dn, dm);

		else

			pr_debug("VFP: itr%d (d%u) = (d%u) op[%u] (d%u)\n",

				 vecitr >> FPSCR_LENGTH_BIT,

				 dd, dn, FOP_TO_IDX(op), dm);

				 dest, dn, FOP_TO_IDX(op), dm);



		except = fop(dd, dn, dm, fpscr);

		except = fop(dest, dn, dm, fpscr);

		pr_debug("VFP: itr%d: exceptions=%08x\n",

			 vecitr >> FPSCR_LENGTH_BIT, except);
@@ -1180,7 +1194,7 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr) 
		 * we encounter an exception.  We continue.

		 */



		dd = FREG_BANK(dd) + ((FREG_IDX(dd) + vecstride) & 6);

		dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 6);

		dn = FREG_BANK(dn) + ((FREG_IDX(dn) + vecstride) & 6);

		if (FREG_BANK(dm) != 0)

			dm = FREG_BANK(dm) + ((FREG_IDX(dm) + vecstride) & 6);

arch/arm/vfp/vfpsingle.c

+22 −11
Original line number Diff line number Diff line
@@ -514,10 +514,6 @@ static u32 vfp_single_fcvtd(int dd, int unused, s32 m, u32 fpscr) 
	else

		vdd.exponent = vsm.exponent + (1023 - 127);



	/*

	 * Technically, if bit 0 of dd is set, this is an invalid

	 * instruction.  However, we ignore this for efficiency.

	 */

	return vfp_double_normaliseround(dd, &vdd, fpscr, exceptions, "fcvtd");



 pack_nan:
@@ -1174,7 +1170,7 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr) 
{

	u32 op = inst & FOP_MASK;

	u32 exceptions = 0;

	unsigned int sd = vfp_get_sd(inst);

	unsigned int dest;

	unsigned int sn = vfp_get_sn(inst);

	unsigned int sm = vfp_get_sm(inst);

	unsigned int vecitr, veclen, vecstride;
@@ -1183,11 +1179,23 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr) 
	veclen = fpscr & FPSCR_LENGTH_MASK;

	vecstride = 1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK);



	/*

	 * fcvtsd takes a dN register number as destination, not sN.

	 * Technically, if bit 0 of dd is set, this is an invalid

	 * instruction.  However, we ignore this for efficiency.

	 * It also only operates on scalars.

	 */

	if ((inst & FEXT_MASK) == FEXT_FCVT) {

		veclen = 0;

		dest = vfp_get_dd(inst);

	} else

		dest = vfp_get_sd(inst);



	/*

	 * If destination bank is zero, vector length is always '1'.

	 * ARM DDI0100F C5.1.3, C5.3.2.

	 */

	if (FREG_BANK(sd) == 0)

	if (FREG_BANK(dest) == 0)

		veclen = 0;



	pr_debug("VFP: vecstride=%u veclen=%u\n", vecstride,
@@ -1201,15 +1209,18 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr) 
		s32 m = vfp_get_float(sm);

		u32 except;



		if (op == FOP_EXT)

		if (op == FOP_EXT && (inst & FEXT_MASK) == FEXT_FCVT)

			pr_debug("VFP: itr%d (d%u) = op[%u] (s%u=%08x)\n",

				 vecitr >> FPSCR_LENGTH_BIT, dest, sn, sm, m);

		else if (op == FOP_EXT)

			pr_debug("VFP: itr%d (s%u) = op[%u] (s%u=%08x)\n",

				 vecitr >> FPSCR_LENGTH_BIT, sd, sn, sm, m);

				 vecitr >> FPSCR_LENGTH_BIT, dest, sn, sm, m);

		else

			pr_debug("VFP: itr%d (s%u) = (s%u) op[%u] (s%u=%08x)\n",

				 vecitr >> FPSCR_LENGTH_BIT, sd, sn,

				 vecitr >> FPSCR_LENGTH_BIT, dest, sn,

				 FOP_TO_IDX(op), sm, m);



		except = fop(sd, sn, m, fpscr);

		except = fop(dest, sn, m, fpscr);

		pr_debug("VFP: itr%d: exceptions=%08x\n",

			 vecitr >> FPSCR_LENGTH_BIT, except);
@@ -1227,7 +1238,7 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr) 
		 * we encounter an exception.  We continue.

		 */



		sd = FREG_BANK(sd) + ((FREG_IDX(sd) + vecstride) & 7);

		dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 7);

		sn = FREG_BANK(sn) + ((FREG_IDX(sn) + vecstride) & 7);

		if (FREG_BANK(sm) != 0)

			sm = FREG_BANK(sm) + ((FREG_IDX(sm) + vecstride) & 7);