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Commit c28c7456 authored by Roland Stigge's avatar Roland Stigge Committed by Florian Tobias Schandinat
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video: Remove pnx4008 driver 



This patch removes the video driver for pnx4008. The architecture is being
removed via the arm-soc tree.

Signed-off-by: default avatarRoland Stigge <stigge@antcom.de>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>
parent a481b37a

drivers/video/Kconfig

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@@ -2151,21 +2151,6 @@ config FB_UDL 
	  mplayer -vo fbdev. Supports all USB 2.0 era DisplayLink devices.

	  To compile as a module, choose M here: the module name is udlfb.



config FB_PNX4008_DUM

	tristate "Display Update Module support on Philips PNX4008 board"

	depends on FB && ARCH_PNX4008

	---help---

	  Say Y here to enable support for PNX4008 Display Update Module (DUM)



config FB_PNX4008_DUM_RGB

	tristate "RGB Framebuffer support on Philips PNX4008 board"

	depends on FB_PNX4008_DUM

	select FB_CFB_FILLRECT

	select FB_CFB_COPYAREA

	select FB_CFB_IMAGEBLIT

	---help---

	  Say Y here to enable support for PNX4008 RGB Framebuffer



config FB_IBM_GXT4500

	tristate "Framebuffer support for IBM GXT4500P adaptor"

	depends on FB && PPC

drivers/video/Makefile

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@@ -128,8 +128,6 @@ obj-$(CONFIG_FB_S3C) += s3c-fb.o 
obj-$(CONFIG_FB_S3C2410)	  += s3c2410fb.o

obj-$(CONFIG_FB_FSL_DIU)	  += fsl-diu-fb.o

obj-$(CONFIG_FB_COBALT)           += cobalt_lcdfb.o

obj-$(CONFIG_FB_PNX4008_DUM)	  += pnx4008/

obj-$(CONFIG_FB_PNX4008_DUM_RGB)  += pnx4008/

obj-$(CONFIG_FB_IBM_GXT4500)	  += gxt4500.o

obj-$(CONFIG_FB_PS3)		  += ps3fb.o

obj-$(CONFIG_FB_SM501)            += sm501fb.o

drivers/video/pnx4008/Makefile

deleted100644 → 0
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#

# Makefile for the new PNX4008 framebuffer device driver

#



obj-$(CONFIG_FB_PNX4008_DUM) += sdum.o

obj-$(CONFIG_FB_PNX4008_DUM_RGB) += pnxrgbfb.o

drivers/video/pnx4008/dum.h

deleted100644 → 0
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/*

 * linux/drivers/video/pnx4008/dum.h

 *

 * Internal header for SDUM

 *

 * 2005 (c) Koninklijke Philips N.V. This file is licensed under

 * the terms of the GNU General Public License version 2. This program

 * is licensed "as is" without any warranty of any kind, whether express

 * or implied.

 */



#ifndef __PNX008_DUM_H__

#define __PNX008_DUM_H__



#include <mach/platform.h>



#define PNX4008_DUMCONF_VA_BASE		IO_ADDRESS(PNX4008_DUMCONF_BASE)

#define PNX4008_DUM_MAIN_VA_BASE	IO_ADDRESS(PNX4008_DUM_MAINCFG_BASE)



/* DUM CFG ADDRESSES */

#define DUM_CH_BASE_ADR		(PNX4008_DUMCONF_VA_BASE + 0x00)

#define DUM_CH_MIN_ADR		(PNX4008_DUMCONF_VA_BASE + 0x00)

#define DUM_CH_MAX_ADR		(PNX4008_DUMCONF_VA_BASE + 0x04)

#define DUM_CH_CONF_ADR		(PNX4008_DUMCONF_VA_BASE + 0x08)

#define DUM_CH_STAT_ADR		(PNX4008_DUMCONF_VA_BASE + 0x0C)

#define DUM_CH_CTRL_ADR		(PNX4008_DUMCONF_VA_BASE + 0x10)



#define CH_MARG		(0x100 / sizeof(u32))

#define DUM_CH_MIN(i)	(*((volatile u32 *)DUM_CH_MIN_ADR + (i) * CH_MARG))

#define DUM_CH_MAX(i)	(*((volatile u32 *)DUM_CH_MAX_ADR + (i) * CH_MARG))

#define DUM_CH_CONF(i)	(*((volatile u32 *)DUM_CH_CONF_ADR + (i) * CH_MARG))

#define DUM_CH_STAT(i)	(*((volatile u32 *)DUM_CH_STAT_ADR + (i) * CH_MARG))

#define DUM_CH_CTRL(i)	(*((volatile u32 *)DUM_CH_CTRL_ADR + (i) * CH_MARG))



#define DUM_CONF_ADR          (PNX4008_DUM_MAIN_VA_BASE + 0x00)

#define DUM_CTRL_ADR          (PNX4008_DUM_MAIN_VA_BASE + 0x04)

#define DUM_STAT_ADR          (PNX4008_DUM_MAIN_VA_BASE + 0x08)

#define DUM_DECODE_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x0C)

#define DUM_COM_BASE_ADR      (PNX4008_DUM_MAIN_VA_BASE + 0x10)

#define DUM_SYNC_C_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x14)

#define DUM_CLK_DIV_ADR       (PNX4008_DUM_MAIN_VA_BASE + 0x18)

#define DUM_DIRTY_LOW_ADR     (PNX4008_DUM_MAIN_VA_BASE + 0x20)

#define DUM_DIRTY_HIGH_ADR    (PNX4008_DUM_MAIN_VA_BASE + 0x24)

#define DUM_FORMAT_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x28)

#define DUM_WTCFG1_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x30)

#define DUM_RTCFG1_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x34)

#define DUM_WTCFG2_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x38)

#define DUM_RTCFG2_ADR        (PNX4008_DUM_MAIN_VA_BASE + 0x3C)

#define DUM_TCFG_ADR          (PNX4008_DUM_MAIN_VA_BASE + 0x40)

#define DUM_OUTP_FORMAT1_ADR  (PNX4008_DUM_MAIN_VA_BASE + 0x44)

#define DUM_OUTP_FORMAT2_ADR  (PNX4008_DUM_MAIN_VA_BASE + 0x48)

#define DUM_SYNC_MODE_ADR     (PNX4008_DUM_MAIN_VA_BASE + 0x4C)

#define DUM_SYNC_OUT_C_ADR    (PNX4008_DUM_MAIN_VA_BASE + 0x50)



#define DUM_CONF              (*(volatile u32 *)(DUM_CONF_ADR))

#define DUM_CTRL              (*(volatile u32 *)(DUM_CTRL_ADR))

#define DUM_STAT              (*(volatile u32 *)(DUM_STAT_ADR))

#define DUM_DECODE            (*(volatile u32 *)(DUM_DECODE_ADR))

#define DUM_COM_BASE          (*(volatile u32 *)(DUM_COM_BASE_ADR))

#define DUM_SYNC_C            (*(volatile u32 *)(DUM_SYNC_C_ADR))

#define DUM_CLK_DIV           (*(volatile u32 *)(DUM_CLK_DIV_ADR))

#define DUM_DIRTY_LOW         (*(volatile u32 *)(DUM_DIRTY_LOW_ADR))

#define DUM_DIRTY_HIGH        (*(volatile u32 *)(DUM_DIRTY_HIGH_ADR))

#define DUM_FORMAT            (*(volatile u32 *)(DUM_FORMAT_ADR))

#define DUM_WTCFG1            (*(volatile u32 *)(DUM_WTCFG1_ADR))

#define DUM_RTCFG1            (*(volatile u32 *)(DUM_RTCFG1_ADR))

#define DUM_WTCFG2            (*(volatile u32 *)(DUM_WTCFG2_ADR))

#define DUM_RTCFG2            (*(volatile u32 *)(DUM_RTCFG2_ADR))

#define DUM_TCFG              (*(volatile u32 *)(DUM_TCFG_ADR))

#define DUM_OUTP_FORMAT1      (*(volatile u32 *)(DUM_OUTP_FORMAT1_ADR))

#define DUM_OUTP_FORMAT2      (*(volatile u32 *)(DUM_OUTP_FORMAT2_ADR))

#define DUM_SYNC_MODE         (*(volatile u32 *)(DUM_SYNC_MODE_ADR))

#define DUM_SYNC_OUT_C        (*(volatile u32 *)(DUM_SYNC_OUT_C_ADR))



/* DUM SLAVE ADDRESSES */

#define DUM_SLAVE_WRITE_ADR      (PNX4008_DUM_MAINCFG_BASE + 0x0000000)

#define DUM_SLAVE_READ1_I_ADR    (PNX4008_DUM_MAINCFG_BASE + 0x1000000)

#define DUM_SLAVE_READ1_R_ADR    (PNX4008_DUM_MAINCFG_BASE + 0x1000004)

#define DUM_SLAVE_READ2_I_ADR    (PNX4008_DUM_MAINCFG_BASE + 0x1000008)

#define DUM_SLAVE_READ2_R_ADR    (PNX4008_DUM_MAINCFG_BASE + 0x100000C)



#define DUM_SLAVE_WRITE_W  ((volatile u32 *)(DUM_SLAVE_WRITE_ADR))

#define DUM_SLAVE_WRITE_HW ((volatile u16 *)(DUM_SLAVE_WRITE_ADR))

#define DUM_SLAVE_READ1_I  ((volatile u8 *)(DUM_SLAVE_READ1_I_ADR))

#define DUM_SLAVE_READ1_R  ((volatile u16 *)(DUM_SLAVE_READ1_R_ADR))

#define DUM_SLAVE_READ2_I  ((volatile u8 *)(DUM_SLAVE_READ2_I_ADR))

#define DUM_SLAVE_READ2_R  ((volatile u16 *)(DUM_SLAVE_READ2_R_ADR))



/* Sony display register addresses */

#define DISP_0_REG            (0x00)

#define DISP_1_REG            (0x01)

#define DISP_CAL_REG          (0x20)

#define DISP_ID_REG           (0x2A)

#define DISP_XMIN_L_REG       (0x30)

#define DISP_XMIN_H_REG       (0x31)

#define DISP_YMIN_REG         (0x32)

#define DISP_XMAX_L_REG       (0x34)

#define DISP_XMAX_H_REG       (0x35)

#define DISP_YMAX_REG         (0x36)

#define DISP_SYNC_EN_REG      (0x38)

#define DISP_SYNC_RISE_L_REG  (0x3C)

#define DISP_SYNC_RISE_H_REG  (0x3D)

#define DISP_SYNC_FALL_L_REG  (0x3E)

#define DISP_SYNC_FALL_H_REG  (0x3F)

#define DISP_PIXEL_REG        (0x0B)

#define DISP_DUMMY1_REG       (0x28)

#define DISP_DUMMY2_REG       (0x29)

#define DISP_TIMING_REG       (0x98)

#define DISP_DUMP_REG         (0x99)



/* Sony display constants */

#define SONY_ID1              (0x22)

#define SONY_ID2              (0x23)



/* Philips display register addresses */

#define PH_DISP_ORIENT_REG    (0x003)

#define PH_DISP_YPOINT_REG    (0x200)

#define PH_DISP_XPOINT_REG    (0x201)

#define PH_DISP_PIXEL_REG     (0x202)

#define PH_DISP_YMIN_REG      (0x406)

#define PH_DISP_YMAX_REG      (0x407)

#define PH_DISP_XMIN_REG      (0x408)

#define PH_DISP_XMAX_REG      (0x409)



/* Misc constants */

#define NO_VALID_DISPLAY_FOUND      (0)

#define DISPLAY2_IS_NOT_CONNECTED   (0)



/* register values */

#define V_BAC_ENABLE		(BIT(0))

#define V_BAC_DISABLE_IDLE	(BIT(1))

#define V_BAC_DISABLE_TRIG	(BIT(2))

#define V_DUM_RESET		(BIT(3))

#define V_MUX_RESET		(BIT(4))

#define BAC_ENABLED		(BIT(0))

#define BAC_DISABLED		0



/* Sony LCD commands */

#define V_LCD_STANDBY_OFF	((BIT(25)) | (0 << 16) | DISP_0_REG)

#define V_LCD_USE_9BIT_BUS	((BIT(25)) | (2 << 16) | DISP_1_REG)

#define V_LCD_SYNC_RISE_L	((BIT(25)) | (0 << 16) | DISP_SYNC_RISE_L_REG)

#define V_LCD_SYNC_RISE_H	((BIT(25)) | (0 << 16) | DISP_SYNC_RISE_H_REG)

#define V_LCD_SYNC_FALL_L	((BIT(25)) | (160 << 16) | DISP_SYNC_FALL_L_REG)

#define V_LCD_SYNC_FALL_H	((BIT(25)) | (0 << 16) | DISP_SYNC_FALL_H_REG)

#define V_LCD_SYNC_ENABLE	((BIT(25)) | (128 << 16) | DISP_SYNC_EN_REG)

#define V_LCD_DISPLAY_ON	((BIT(25)) | (64 << 16) | DISP_0_REG)



enum {

	PAD_NONE,

	PAD_512,

	PAD_1024

};



enum {

	RGB888,

	RGB666,

	RGB565,

	BGR565,

	ARGB1555,

	ABGR1555,

	ARGB4444,

	ABGR4444

};



struct dum_setup {

	int sync_neg_edge;

	int round_robin;

	int mux_int;

	int synced_dirty_flag_int;

	int dirty_flag_int;

	int error_int;

	int pf_empty_int;

	int sf_empty_int;

	int bac_dis_int;

	u32 dirty_base_adr;

	u32 command_base_adr;

	u32 sync_clk_div;

	int sync_output;

	u32 sync_restart_val;

	u32 set_sync_high;

	u32 set_sync_low;

};



struct dum_ch_setup {

	int disp_no;

	u32 xmin;

	u32 ymin;

	u32 xmax;

	u32 ymax;

	int xmirror;

	int ymirror;

	int rotate;

	u32 minadr;

	u32 maxadr;

	u32 dirtybuffer;

	int pad;

	int format;

	int hwdirty;

	int slave_trans;

};



struct disp_window {

	u32 xmin_l;

	u32 xmin_h;

	u32 ymin;

	u32 xmax_l;

	u32 xmax_h;

	u32 ymax;

};



#endif				/* #ifndef __PNX008_DUM_H__ */

drivers/video/pnx4008/fbcommon.h

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/*

 * Copyright (C) 2005 Philips Semiconductors

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2, or (at your option)

 * any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; see the file COPYING.  If not, write to

 * the Free Software Foundation, Inc., 59 Temple Place - Suite 330,

 * Boston, MA 02111-1307, USA, or http://www.gnu.org/licenses/gpl.html

*/



#define QCIF_W  (176)

#define QCIF_H  (144)



#define CIF_W   (352)

#define CIF_H   (288)



#define LCD_X_RES	208

#define LCD_Y_RES	320

#define LCD_X_PAD	256

#define LCD_BBP		4	/* Bytes Per Pixel */



#define DISP_MAX_X_SIZE     (320)

#define DISP_MAX_Y_SIZE     (208)



#define RETURNVAL_BASE (0x400)



enum fb_ioctl_returntype {

	ENORESOURCESLEFT = RETURNVAL_BASE,

	ERESOURCESNOTFREED,

	EPROCNOTOWNER,

	EFBNOTOWNER,

	ECOPYFAILED,

	EIOREMAPFAILED,

};