Loading drivers/spi/spi-imx.c +2 −15 Original line number Original line Diff line number Diff line Loading @@ -204,8 +204,8 @@ static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, { { struct spi_imx_data *spi_imx = spi_master_get_devdata(master); struct spi_imx_data *spi_imx = spi_master_get_devdata(master); if (spi_imx->dma_is_inited && if (spi_imx->dma_is_inited && transfer->len >= spi_imx->wml && transfer->len > spi_imx->wml * sizeof(u32)) (transfer->len % spi_imx->wml) == 0) return true; return true; return false; return false; } } Loading Loading @@ -919,8 +919,6 @@ static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; int ret; int ret; unsigned long timeout; unsigned long timeout; u32 dma; int left; struct spi_master *master = spi_imx->bitbang.master; struct spi_master *master = spi_imx->bitbang.master; struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; Loading Loading @@ -954,13 +952,6 @@ static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, /* Trigger the cspi module. */ /* Trigger the cspi module. */ spi_imx->dma_finished = 0; spi_imx->dma_finished = 0; dma = readl(spi_imx->base + MX51_ECSPI_DMA); dma = dma & (~MX51_ECSPI_DMA_RXT_WML_MASK); /* Change RX_DMA_LENGTH trigger dma fetch tail data */ left = transfer->len % spi_imx->wml; if (left) writel(dma | (left << MX51_ECSPI_DMA_RXT_WML_OFFSET), spi_imx->base + MX51_ECSPI_DMA); /* /* * Set these order to avoid potential RX overflow. The overflow may * Set these order to avoid potential RX overflow. The overflow may * happen if we enable SPI HW before starting RX DMA due to rescheduling * happen if we enable SPI HW before starting RX DMA due to rescheduling Loading Loading @@ -992,10 +983,6 @@ static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, spi_imx->devtype_data->reset(spi_imx); spi_imx->devtype_data->reset(spi_imx); dmaengine_terminate_all(master->dma_rx); dmaengine_terminate_all(master->dma_rx); } } dma &= ~MX51_ECSPI_DMA_RXT_WML_MASK; writel(dma | spi_imx->wml << MX51_ECSPI_DMA_RXT_WML_OFFSET, spi_imx->base + MX51_ECSPI_DMA); } } spi_imx->dma_finished = 1; spi_imx->dma_finished = 1; Loading Loading
drivers/spi/spi-imx.c +2 −15 Original line number Original line Diff line number Diff line Loading @@ -204,8 +204,8 @@ static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, { { struct spi_imx_data *spi_imx = spi_master_get_devdata(master); struct spi_imx_data *spi_imx = spi_master_get_devdata(master); if (spi_imx->dma_is_inited && if (spi_imx->dma_is_inited && transfer->len >= spi_imx->wml && transfer->len > spi_imx->wml * sizeof(u32)) (transfer->len % spi_imx->wml) == 0) return true; return true; return false; return false; } } Loading Loading @@ -919,8 +919,6 @@ static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; int ret; int ret; unsigned long timeout; unsigned long timeout; u32 dma; int left; struct spi_master *master = spi_imx->bitbang.master; struct spi_master *master = spi_imx->bitbang.master; struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; Loading Loading @@ -954,13 +952,6 @@ static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, /* Trigger the cspi module. */ /* Trigger the cspi module. */ spi_imx->dma_finished = 0; spi_imx->dma_finished = 0; dma = readl(spi_imx->base + MX51_ECSPI_DMA); dma = dma & (~MX51_ECSPI_DMA_RXT_WML_MASK); /* Change RX_DMA_LENGTH trigger dma fetch tail data */ left = transfer->len % spi_imx->wml; if (left) writel(dma | (left << MX51_ECSPI_DMA_RXT_WML_OFFSET), spi_imx->base + MX51_ECSPI_DMA); /* /* * Set these order to avoid potential RX overflow. The overflow may * Set these order to avoid potential RX overflow. The overflow may * happen if we enable SPI HW before starting RX DMA due to rescheduling * happen if we enable SPI HW before starting RX DMA due to rescheduling Loading Loading @@ -992,10 +983,6 @@ static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, spi_imx->devtype_data->reset(spi_imx); spi_imx->devtype_data->reset(spi_imx); dmaengine_terminate_all(master->dma_rx); dmaengine_terminate_all(master->dma_rx); } } dma &= ~MX51_ECSPI_DMA_RXT_WML_MASK; writel(dma | spi_imx->wml << MX51_ECSPI_DMA_RXT_WML_OFFSET, spi_imx->base + MX51_ECSPI_DMA); } } spi_imx->dma_finished = 1; spi_imx->dma_finished = 1; Loading