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Commit c127562a authored by Gavin Shan's avatar Gavin Shan Committed by Michael Ellerman
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powerpc/powernv: Increase PE# capacity



Each PHB maintains an array helping to translate 2-bytes Request
ID (RID) to PE# with the assumption that PE# takes one byte, meaning
that we can't have more than 256 PEs. However, pci_dn->pe_number
already had 4-bytes for the PE#.

This extends the PE# capacity for every PHB. After that, the PE number
is represented by 4-bytes value. Then we can reuse IODA_INVALID_PE to
check the PE# in phb->pe_rmap[] is valid or not.

Signed-off-by: default avatarGavin Shan <gwshan@linux.vnet.ibm.com>
Reviewed-by: default avatarDaniel Axtens <dja@axtens.net>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 577c8c88
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+5 −1
Original line number Diff line number Diff line
@@ -761,7 +761,7 @@ static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)

	/* Clear the reverse map */
	for (rid = pe->rid; rid < rid_end; rid++)
		phb->ioda.pe_rmap[rid] = 0;
		phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;

	/* Release from all parents PELT-V */
	while (parent) {
@@ -3492,6 +3492,10 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np,
	if (prop32)
		phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);

	/* Invalidate RID to PE# mapping */
	for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
		phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;

	/* Parse 64-bit MMIO range */
	pnv_ioda_parse_m64_window(phb);

+2 −5
Original line number Diff line number Diff line
@@ -152,11 +152,8 @@ struct pnv_phb {
		struct list_head	pe_list;
		struct mutex            pe_list_mutex;

		/* Reverse map of PEs, will have to extend if
		 * we are to support more than 256 PEs, indexed
		 * bus { bus, devfn }
		 */
		unsigned char		pe_rmap[0x10000];
		/* Reverse map of PEs, indexed by {bus, devfn} */
		unsigned int		pe_rmap[0x10000];

		/* TCE cache invalidate registers (physical and
		 * remapped)