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Commit c0feb268 authored by Marek Szyprowski's avatar Marek Szyprowski Committed by Sylwester Nawrocki
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clk: samsung: exynos542x: add missing parent GSCL block clocks 



This patch adds clocks, which are required for preserving parent clock
configuration on GSCL power domain on/off.

Signed-off-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
parent 9f9499ae

drivers/clk/samsung/clk-exynos5420.c

+4 −4
Original line number Diff line number Diff line
@@ -677,8 +677,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { 
			SRC_TOP5, 20, 1),

	MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",

			mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),

	MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p,

			SRC_TOP5, 28, 1),

	MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl",

			mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),



	MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),

	MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
@@ -729,8 +729,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { 
			SRC_TOP12, 20, 1),

	MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",

			mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1),

	MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p,

			SRC_TOP12, 28, 1),

	MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl",

			mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1),



	/* DISP1 Block */

	MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),

include/dt-bindings/clock/exynos5420.h

+2 −0
Original line number Diff line number Diff line
@@ -210,6 +210,8 @@ 
#define CLK_MOUT_SW_ACLK300     649

#define CLK_MOUT_USER_ACLK400_DISP1     650

#define CLK_MOUT_SW_ACLK400     651

#define CLK_MOUT_USER_ACLK300_GSCL	652

#define CLK_MOUT_SW_ACLK300_GSCL	653



/* divider clocks */

#define CLK_DOUT_PIXEL		768