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Commit be6d4321 authored by Jean-Christophe PLAGNIOL-VILLARD's avatar Jean-Christophe PLAGNIOL-VILLARD
Browse files

ARM: at91: make aic soc independent 



on all at91 have the Advanced Interrupt Controller starts at address
0xfffff000

Signed-off-by: default avatarJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: default avatarNicolas Ferre <nicolas.ferre@atmel.com>
parent 13079a73

arch/arm/mach-at91/include/mach/at91_aic.h

+30 −18
Original line number Diff line number Diff line
@@ -16,7 +16,19 @@ 
#ifndef AT91_AIC_H

#define AT91_AIC_H



#define AT91_AIC_SMR(n)		(AT91_AIC + ((n) * 4))	/* Source Mode Registers 0-31 */

#ifndef __ASSEMBLY__

extern void __iomem *at91_aic_base;



#define at91_aic_read(field) \

	__raw_readl(at91_aic_base + field)



#define at91_aic_write(field, value) \

	__raw_writel(value, at91_aic_base + field);

#else

.extern at91_aic_base

#endif



#define AT91_AIC_SMR(n)		((n) * 4)		/* Source Mode Registers 0-31 */

#define		AT91_AIC_PRIOR		(7 << 0)		/* Priority Level */

#define		AT91_AIC_SRCTYPE	(3 << 5)		/* Interrupt Source Type */

#define			AT91_AIC_SRCTYPE_LOW		(0 << 5)
@@ -24,30 +36,30 @@ 
#define			AT91_AIC_SRCTYPE_HIGH		(2 << 5)

#define			AT91_AIC_SRCTYPE_RISING		(3 << 5)



#define AT91_AIC_SVR(n)		(AT91_AIC + 0x80 + ((n) * 4))	/* Source Vector Registers 0-31 */

#define AT91_AIC_IVR		(AT91_AIC + 0x100)	/* Interrupt Vector Register */

#define AT91_AIC_FVR		(AT91_AIC + 0x104)	/* Fast Interrupt Vector Register */

#define AT91_AIC_ISR		(AT91_AIC + 0x108)	/* Interrupt Status Register */

#define AT91_AIC_SVR(n)		(0x80 + ((n) * 4))	/* Source Vector Registers 0-31 */

#define AT91_AIC_IVR		0x100			/* Interrupt Vector Register */

#define AT91_AIC_FVR		0x104			/* Fast Interrupt Vector Register */

#define AT91_AIC_ISR		0x108			/* Interrupt Status Register */

#define		AT91_AIC_IRQID		(0x1f << 0)		/* Current Interrupt Identifier */



#define AT91_AIC_IPR		(AT91_AIC + 0x10c)	/* Interrupt Pending Register */

#define AT91_AIC_IMR		(AT91_AIC + 0x110)	/* Interrupt Mask Register */

#define AT91_AIC_CISR		(AT91_AIC + 0x114)	/* Core Interrupt Status Register */

#define AT91_AIC_IPR		0x10c			/* Interrupt Pending Register */

#define AT91_AIC_IMR		0x110			/* Interrupt Mask Register */

#define AT91_AIC_CISR		0x114			/* Core Interrupt Status Register */

#define		AT91_AIC_NFIQ		(1 << 0)		/* nFIQ Status */

#define		AT91_AIC_NIRQ		(1 << 1)		/* nIRQ Status */



#define AT91_AIC_IECR		(AT91_AIC + 0x120)	/* Interrupt Enable Command Register */

#define AT91_AIC_IDCR		(AT91_AIC + 0x124)	/* Interrupt Disable Command Register */

#define AT91_AIC_ICCR		(AT91_AIC + 0x128)	/* Interrupt Clear Command Register */

#define AT91_AIC_ISCR		(AT91_AIC + 0x12c)	/* Interrupt Set Command Register */

#define AT91_AIC_EOICR		(AT91_AIC + 0x130)	/* End of Interrupt Command Register */

#define AT91_AIC_SPU		(AT91_AIC + 0x134)	/* Spurious Interrupt Vector Register */

#define AT91_AIC_DCR		(AT91_AIC + 0x138)	/* Debug Control Register */

#define AT91_AIC_IECR		0x120			/* Interrupt Enable Command Register */

#define AT91_AIC_IDCR		0x124			/* Interrupt Disable Command Register */

#define AT91_AIC_ICCR		0x128			/* Interrupt Clear Command Register */

#define AT91_AIC_ISCR		0x12c			/* Interrupt Set Command Register */

#define AT91_AIC_EOICR		0x130			/* End of Interrupt Command Register */

#define AT91_AIC_SPU		0x134			/* Spurious Interrupt Vector Register */

#define AT91_AIC_DCR		0x138			/* Debug Control Register */

#define		AT91_AIC_DCR_PROT	(1 << 0)		/* Protection Mode */

#define		AT91_AIC_DCR_GMSK	(1 << 1)		/* General Mask */



#define AT91_AIC_FFER		(AT91_AIC + 0x140)	/* Fast Forcing Enable Register [SAM9 only] */

#define AT91_AIC_FFDR		(AT91_AIC + 0x144)	/* Fast Forcing Disable Register [SAM9 only] */

#define AT91_AIC_FFSR		(AT91_AIC + 0x148)	/* Fast Forcing Status Register [SAM9 only] */

#define AT91_AIC_FFER		0x140			/* Fast Forcing Enable Register [SAM9 only] */

#define AT91_AIC_FFDR		0x144			/* Fast Forcing Disable Register [SAM9 only] */

#define AT91_AIC_FFSR		0x148			/* Fast Forcing Status Register [SAM9 only] */



#endif

arch/arm/mach-at91/include/mach/at91cap9.h

+0 −1
Original line number Diff line number Diff line
@@ -82,7 +82,6 @@ 
#define AT91_BCRAMC	(0xffffe400 - AT91_BASE_SYS)

#define AT91_DDRSDRC0	(0xffffe600 - AT91_BASE_SYS)

#define AT91_MATRIX	(0xffffea00 - AT91_BASE_SYS)

#define AT91_AIC	(0xfffff000 - AT91_BASE_SYS)

#define AT91_PMC	(0xfffffc00 - AT91_BASE_SYS)

#define AT91_RSTC	(0xfffffd00 - AT91_BASE_SYS)

#define AT91_GPBR	(cpu_is_at91cap9_revB() ?	\

arch/arm/mach-at91/include/mach/at91rm9200.h

+0 −1
Original line number Diff line number Diff line
@@ -79,7 +79,6 @@ 
/*

 * System Peripherals (offset from AT91_BASE_SYS)

 */

#define AT91_AIC	(0xfffff000 - AT91_BASE_SYS)	/* Advanced Interrupt Controller */

#define AT91_PMC	(0xfffffc00 - AT91_BASE_SYS)	/* Power Management Controller */

#define AT91_ST		(0xfffffd00 - AT91_BASE_SYS)	/* System Timer */

#define AT91_RTC	(0xfffffe00 - AT91_BASE_SYS)	/* Real-Time Clock */

arch/arm/mach-at91/include/mach/at91sam9260.h

+0 −1
Original line number Diff line number Diff line
@@ -82,7 +82,6 @@ 
 */

#define AT91_SDRAMC0	(0xffffea00 - AT91_BASE_SYS)

#define AT91_MATRIX	(0xffffee00 - AT91_BASE_SYS)

#define AT91_AIC	(0xfffff000 - AT91_BASE_SYS)

#define AT91_PMC	(0xfffffc00 - AT91_BASE_SYS)

#define AT91_RSTC	(0xfffffd00 - AT91_BASE_SYS)

#define AT91_GPBR	(0xfffffd50 - AT91_BASE_SYS)

arch/arm/mach-at91/include/mach/at91sam9261.h

+0 −1
Original line number Diff line number Diff line
@@ -67,7 +67,6 @@ 
 */

#define AT91_SDRAMC0	(0xffffea00 - AT91_BASE_SYS)

#define AT91_MATRIX	(0xffffee00 - AT91_BASE_SYS)

#define AT91_AIC	(0xfffff000 - AT91_BASE_SYS)

#define AT91_PMC	(0xfffffc00 - AT91_BASE_SYS)

#define AT91_RSTC	(0xfffffd00 - AT91_BASE_SYS)

#define AT91_GPBR	(0xfffffd50 - AT91_BASE_SYS)