Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit bdd57d03 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Add scaled paramater to update_sprite_watermarks() 



For calculating watermarks we want to know whether sprites are
scaled. Pass that information to update_sprite_watermarks() so that
eventually we may do some watermark pre-computing.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 2c1792a1

drivers/gpu/drm/i915/i915_drv.h

+1 −1
Original line number Diff line number Diff line
@@ -361,7 +361,7 @@ struct drm_i915_display_funcs { 
	void (*update_wm)(struct drm_device *dev);

	void (*update_sprite_wm)(struct drm_device *dev, int pipe,

				 uint32_t sprite_width, int pixel_size,

				 bool enable);

				 bool enable, bool scaled);

	void (*modeset_global_resources)(struct drm_device *dev);

	/* Returns the active state of the crtc, and if the crtc is active,

	 * fills out the pipe-config with the hw state. */

drivers/gpu/drm/i915/intel_drv.h

+4 −3
Original line number Diff line number Diff line
@@ -349,7 +349,8 @@ struct intel_plane { 
	 * for the watermark calculations. Currently only Haswell uses this.

	 */

	struct {

		bool enable;

		bool enabled;

		bool scaled;

		uint8_t bytes_per_pixel;

		uint32_t horiz_pixels;

	} wm;
@@ -770,8 +771,8 @@ extern void intel_ddi_init(struct drm_device *dev, enum port port); 
/* For use by IVB LP watermark workaround in intel_sprite.c */

extern void intel_update_watermarks(struct drm_device *dev);

extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,

					   uint32_t sprite_width,

					   int pixel_size, bool enable);

					   uint32_t sprite_width, int pixel_size,

					   bool enabled, bool scaled);



extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,

						    unsigned int tiling_mode,

drivers/gpu/drm/i915/intel_pm.c

+7 −6
Original line number Diff line number Diff line
@@ -2403,7 +2403,7 @@ static void hsw_compute_wm_parameters(struct drm_device *dev, 
		pipe = intel_plane->pipe;

		p = &params[pipe];



		p->sprite_enabled = intel_plane->wm.enable;

		p->sprite_enabled = intel_plane->wm.enabled;

		p->spr_bytes_per_pixel = intel_plane->wm.bytes_per_pixel;

		p->spr_horiz_pixels = intel_plane->wm.horiz_pixels;
@@ -2631,7 +2631,7 @@ static void haswell_update_wm(struct drm_device *dev) 


static void haswell_update_sprite_wm(struct drm_device *dev, int pipe,

				     uint32_t sprite_width, int pixel_size,

				     bool enable)

				     bool enabled, bool scaled)

{

	struct drm_plane *plane;
@@ -2639,7 +2639,8 @@ static void haswell_update_sprite_wm(struct drm_device *dev, int pipe, 
		struct intel_plane *intel_plane = to_intel_plane(plane);



		if (intel_plane->pipe == pipe) {

			intel_plane->wm.enable = enable;

			intel_plane->wm.enabled = enabled;

			intel_plane->wm.scaled = scaled;

			intel_plane->wm.horiz_pixels = sprite_width + 1;

			intel_plane->wm.bytes_per_pixel = pixel_size;

			break;
@@ -2727,7 +2728,7 @@ sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane, 


static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,

					 uint32_t sprite_width, int pixel_size,

					 bool enable)

					 bool enable, bool scaled)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int latency = SNB_READ_WM0_LATENCY() * 100;	/* In unit 0.1us */
@@ -2850,13 +2851,13 @@ void intel_update_watermarks(struct drm_device *dev) 


void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,

				    uint32_t sprite_width, int pixel_size,

				    bool enable)

				    bool enable, bool scaled)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	if (dev_priv->display.update_sprite_wm)

		dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,

						   pixel_size, enable);

						   pixel_size, enable, scaled);

}



static struct drm_i915_gem_object *

drivers/gpu/drm/i915/intel_sprite.c

+7 −4
Original line number Diff line number Diff line
@@ -114,7 +114,8 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_framebuffer *fb, 
	crtc_w--;

	crtc_h--;



	intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true);

	intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true,

				       src_w != crtc_w || src_h != crtc_h);



	I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);

	I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
@@ -268,7 +269,8 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, 
	crtc_w--;

	crtc_h--;



	intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true);

	intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true,

				       src_w != crtc_w || src_h != crtc_h);



	/*

	 * IVB workaround: must disable low power watermarks for at least
@@ -336,7 +338,7 @@ ivb_disable_plane(struct drm_plane *plane) 


	dev_priv->sprite_scaling_enabled &= ~(1 << pipe);



	intel_update_sprite_watermarks(dev, pipe, 0, 0, false);

	intel_update_sprite_watermarks(dev, pipe, 0, 0, false, false);



	/* potentially re-enable LP watermarks */

	if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled)
@@ -456,7 +458,8 @@ ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, 
	crtc_w--;

	crtc_h--;



	intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true);

	intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true,

				       src_w != crtc_w || src_h != crtc_h);



	dvsscale = 0;

	if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h)