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Commit bd698cf6 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'pinctrl-v3.16-1' of... 

Merge tag 'pinctrl-v3.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl into next

Pull pin control changes from Linus Walleij:
 "This is the bulk of pin control changes for the v3.16 development
  cycle:

   - Antoine Tenart made the get_group_pins() vtable entry optional.

   - Antoine also provides an entirely new driver for the Marvell Berlin
     SoC.  This is unrelated to the existing MVEBU hardware driver and
     warrants its own separate driver.

   - reflected from the GPIO subsystem there is a number of refactorings
     to make pin control drivers with gpiochips use the new gpiolib
     irqchip helpers.  The following drivers were converted to use the
     new infrastructure:
       * ST Microelectronics STiH416 and friends
       * The Atmel AT91
       * The CSR SiRF (Prima2)
       * The Qualcomm MSM series

   - massive improvements in the Qualcomm MSM driver from Bjorn
     Andersson, Andy Gross and Kumar Gala.  Among those new support for
     the IPQ8064 and MSM8x74 SoC variants.

   - support for the Freescale i.MX6 SoloX SoC variant.

   - massive improvements in the Allwinner sunxi driver from Boris
     Brezillon, Maxime Ripard and Chen-Yu Tsai.

   - Renesas PFC updates from Laurent Pinchart, Kuninori Morimoto,
     Wolfram Sang and Magnus Damm.

   - Cleanups and refactorings of the nVidia Tegra driver from Stepgen
     Warren.

   - the Exynos driver now supports the Exynos3250 SoC.

   - Intel BayTrail updates from Jin Yao, Mika Westerberg.

   - the MVEBU driver now supports the Orion5x SoC variants, which is
     part of the effort of getting rid of the old Marvell kludges in
     arch/arm/mach-orion5x

   - Rockchip driver updates from Heiko Stuebner.

   - a ton of cleanups and janitorial patches from Axel Lin.

   - some minor fixes and improvements here and there"

* tag 'pinctrl-v3.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (93 commits)
  pinctrl: sirf: fix a bad conflict resolution
  pinctrl: msm: Add more MSM8X74 pin definitions
  pinctrl: qcom: ipq8064: Fix naming convention
  pinctrl: msm: Add missing sdc1 and sdc3 groups
  pinctrl: sirf: switch to using allocated state container
  pinctrl: Enable "power-source" to be extracted from DT files
  pinctrl: sunxi: create irq/pin mapping during init
  pinctrl: pinconf-generic: Use kmemdup instead of kmalloc + memcpy
  pinctrl: berlin: Use devm_ioremap_resource()
  pinctrl: sirf: fix typo for GPIO bank number
  pinctrl: sunxi: depend on RESET_CONTROLLER
  pinctrl: sunxi: fix pin numbers passed to register offset helpers
  pinctrl: add pinctrl driver for imx6sx
  pinctrl/at91: Fix lockup when IRQ on PIOC and PIOD occurs
  pinctrl: msm: switch to using generic GPIO irqchip helpers
  pinctrl: sunxi: Fix multiple registration issue
  pinctrl: sunxi: Fix recursive dependency
  pinctrl: berlin: add the BG2CD pinctrl driver
  pinctrl: berlin: add the BG2 pinctrl driver
  pinctrl: berlin: add the BG2Q pinctrl driver
  ...
parents f4562052 29c7f1f5

Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt

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Original line number Diff line number Diff line
@@ -6,8 +6,13 @@ the first two functions being GPIO in and out. The configuration on 
the pins includes drive strength and pull-up.



Required properties:

- compatible: "allwinner,<soc>-pinctrl". Supported SoCs for now are:

  sun5i-a13.

- compatible: Should be one of the followings (depending on you SoC):

  "allwinner,sun4i-a10-pinctrl"

  "allwinner,sun5i-a10s-pinctrl"

  "allwinner,sun5i-a13-pinctrl"

  "allwinner,sun6i-a31-pinctrl"

  "allwinner,sun6i-a31-r-pinctrl"

  "allwinner,sun7i-a20-pinctrl"

- reg: Should contain the register physical address and length for the

  pin controller.

Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt

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* Freescale i.MX6 SoloX IOMUX Controller



Please refer to fsl,imx-pinctrl.txt in this directory for common binding part

and usage.



Required properties:

- compatible: "fsl,imx6sx-iomuxc"

- fsl,pins: each entry consists of 6 integers and represents the mux and config

  setting for one pin.  The first 5 integers <mux_reg conf_reg input_reg mux_val

  input_val> are specified using a PIN_FUNC_ID macro, which can be found in

  imx6sx-pinfunc.h under device tree source folder.  The last integer CONFIG is

  the pad setting value like pull-up on this pin.  Please refer to i.MX6 SoloX

  Reference Manual for detailed CONFIG settings.



CONFIG bits definition:

PAD_CTL_HYS                     (1 << 16)

PAD_CTL_PUS_100K_DOWN           (0 << 14)

PAD_CTL_PUS_47K_UP              (1 << 14)

PAD_CTL_PUS_100K_UP             (2 << 14)

PAD_CTL_PUS_22K_UP              (3 << 14)

PAD_CTL_PUE                     (1 << 13)

PAD_CTL_PKE                     (1 << 12)

PAD_CTL_ODE                     (1 << 11)

PAD_CTL_SPEED_LOW               (0 << 6)

PAD_CTL_SPEED_MED               (1 << 6)

PAD_CTL_SPEED_HIGH              (3 << 6)

PAD_CTL_DSE_DISABLE             (0 << 3)

PAD_CTL_DSE_260ohm              (1 << 3)

PAD_CTL_DSE_130ohm              (2 << 3)

PAD_CTL_DSE_87ohm               (3 << 3)

PAD_CTL_DSE_65ohm               (4 << 3)

PAD_CTL_DSE_52ohm               (5 << 3)

PAD_CTL_DSE_43ohm               (6 << 3)

PAD_CTL_DSE_37ohm               (7 << 3)

PAD_CTL_SRE_FAST                (1 << 0)

PAD_CTL_SRE_SLOW                (0 << 0)

Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt

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* Marvell Orion SoC pinctrl driver for mpp



Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding

part and usage.



Required properties:

- compatible: "marvell,88f5181l-pinctrl", "marvell,88f5182-pinctrl",

              "marvell,88f5281-pinctrl"



- reg: two register areas, the first one describing the first two

  contiguous MPP registers, and the second one describing the single

  final MPP register, separated from the previous one.



Available mpp pins/groups and functions:

Note: brackets (x) are not part of the mpp name for marvell,function and given

only for more detailed description in this document.



* Marvell Orion 88f5181l



name          pins     functions

================================================================================

mpp0          0        pcie(rstout), pci(req2), gpio

mpp1          1        gpio, pci(gnt2)

mpp2          2        gpio, pci(req3), pci-1(pme)

mpp3          3        gpio, pci(gnt3)

mpp4          4        gpio, pci(req4)

mpp5          5        gpio, pci(gnt4)

mpp6          6        gpio, pci(req5), pci-1(clk)

mpp7          7        gpio, pci(gnt5), pci-1(clk)

mpp8          8        gpio, ge(col)

mpp9          9        gpio, ge(rxerr)

mpp10         10       gpio, ge(crs)

mpp11         11       gpio, ge(txerr)

mpp12         12       gpio, ge(txd4)

mpp13         13       gpio, ge(txd5)

mpp14         14       gpio, ge(txd6)

mpp15         15       gpio, ge(txd7)

mpp16         16       ge(rxd4)

mpp17         17       ge(rxd5)

mpp18         18       ge(rxd6)

mpp19         19       ge(rxd7)



* Marvell Orion 88f5182



name          pins     functions

================================================================================

mpp0          0        pcie(rstout), pci(req2), gpio

mpp1          1        gpio, pci(gnt2)

mpp2          2        gpio, pci(req3), pci-1(pme)

mpp3          3        gpio, pci(gnt3)

mpp4          4        gpio, pci(req4), bootnand(re), sata0(prsnt)

mpp5          5        gpio, pci(gnt4), bootnand(we), sata1(prsnt)

mpp6          6        gpio, pci(req5), nand(re0), sata0(act)

mpp7          7        gpio, pci(gnt5), nand(we0), sata1(act)

mpp8          8        gpio, ge(col)

mpp9          9        gpio, ge(rxerr)

mpp10         10       gpio, ge(crs)

mpp11         11       gpio, ge(txerr)

mpp12         12       gpio, ge(txd4), nand(re1), sata0(ledprsnt)

mpp13         13       gpio, ge(txd5), nand(we1), sata1(ledprsnt)

mpp14         14       gpio, ge(txd6), nand(re2), sata0(ledact)

mpp15         15       gpio, ge(txd7), nand(we2), sata1(ledact)

mpp16         16       uart1(rxd), ge(rxd4), gpio

mpp17         17       uart1(txd), ge(rxd5), gpio

mpp18         18       uart1(cts), ge(rxd6), gpio

mpp19         19       uart1(rts), ge(rxd7), gpio



* Marvell Orion 88f5281



name          pins     functions

================================================================================

mpp0          0        pcie(rstout), pci(req2), gpio

mpp1          1        gpio, pci(gnt2)

mpp2          2        gpio, pci(req3), pci(pme)

mpp3          3        gpio, pci(gnt3)

mpp4          4        gpio, pci(req4), bootnand(re)

mpp5          5        gpio, pci(gnt4), bootnand(we)

mpp6          6        gpio, pci(req5), nand(re0)

mpp7          7        gpio, pci(gnt5), nand(we0)

mpp8          8        gpio, ge(col)

mpp9          9        gpio, ge(rxerr)

mpp10         10       gpio, ge(crs)

mpp11         11       gpio, ge(txerr)

mpp12         12       gpio, ge(txd4), nand(re1)

mpp13         13       gpio, ge(txd5), nand(we1)

mpp14         14       gpio, ge(txd6), nand(re2)

mpp15         15       gpio, ge(txd7), nand(we2)

mpp16         16       uart1(rxd), ge(rxd4)

mpp17         17       uart1(txd), ge(rxd5)

mpp18         18       uart1(cts), ge(rxd6)

mpp19         19       uart1(rts), ge(rxd7)

Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt

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@@ -156,6 +156,7 @@ input-disable - disable input on pin (no effect on output) 
input-schmitt-enable	- enable schmitt-trigger mode

input-schmitt-disable	- disable schmitt-trigger mode

input-debounce		- debounce mode with debound time X

power-source		- select between different power supplies

low-power-enable	- enable low power mode

low-power-disable	- disable low power mode

output-low		- set the pin to output mode with low level

Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt

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Qualcomm APQ8064 TLMM block



Required properties:

- compatible: "qcom,apq8064-pinctrl"

- reg: Should be the base address and length of the TLMM block.

- interrupts: Should be the parent IRQ of the TLMM block.

- interrupt-controller: Marks the device node as an interrupt controller.

- #interrupt-cells: Should be two.

- gpio-controller: Marks the device node as a GPIO controller.

- #gpio-cells : Should be two.

                The first cell is the gpio pin number and the

                second cell is used for optional parameters.



Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for

a general description of GPIO and interrupt bindings.



Please refer to pinctrl-bindings.txt in this directory for details of the

common pinctrl bindings used by client devices, including the meaning of the

phrase "pin configuration node".



Qualcomm's pin configuration nodes act as a container for an abitrary number of

subnodes. Each of these subnodes represents some desired configuration for a

pin, a group, or a list of pins or groups. This configuration can include the

mux function to select on those pin(s)/group(s), and various pin configuration

parameters, such as pull-up, drive strength, etc.



The name of each subnode is not important; all subnodes should be enumerated

and processed purely based on their content.



Each subnode only affects those parameters that are explicitly listed. In

other words, a subnode that lists a mux function but no pin configuration

parameters implies no information about any pin configuration parameters.

Similarly, a pin subnode that describes a pullup parameter implies no

information about e.g. the mux function.





The following generic properties as defined in pinctrl-bindings.txt are valid

to specify in a pin configuration subnode:



 pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength,

 output-low, output-high.



Non-empty subnodes must specify the 'pins' property.



Valid values for pins are:

  gpio0-gpio89



Valid values for function are:

  cam_mclk, codec_mic_i2s, codec_spkr_i2s, gsbi1, gsbi2, gsbi3, gsbi4,

  gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6,

  gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1,

  gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm,

  riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic,



Example:



	msmgpio: pinctrl@800000 {

		compatible = "qcom,apq8064-pinctrl";

		reg = <0x800000 0x4000>;



		gpio-controller;

		#gpio-cells = <2>;

		interrupt-controller;

		#interrupt-cells = <2>;

		interrupts = <0 32 0x4>;



		pinctrl-names = "default";

		pinctrl-0 = <&gsbi5_uart_default>;



		gsbi5_uart_default: gsbi5_uart_default {

			mux {

				pins = "gpio51", "gpio52";

				function = "gsbi5";

			};



			tx {

				pins = "gpio51";

				drive-strength = <4>;

				bias-disable;

			};



			rx {

				pins = "gpio52";

				drive-strength = <2>;

				bias-pull-up;

			};

		};

	};