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Commit bc752862 authored by Chris Wilson's avatar Chris Wilson Committed by Daniel Vetter
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drm/i915: Handle untiled planes when computing their offsets 

We trim the fb to fit the CRTC by computing the offset of that CRTC to
its nearest tile_row origin. This allows us to use framebuffers that are
larger than the CRTC limits without additional work.

However, we failed to compute the offset for a linear framebuffer
correctly as we treated its x-advance in whole tiles (instead of the
linear increment expected), leaving the CRTC misaligned with its
contents.

Fixes regression from commit c2c75131
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Thu Jul 5 12:17:30 2012 +0200

    drm/i915: adjust framebuffer base address on gen4+

v2: Adjust relative x-coordinate after linear alignment (vsyrjala)
v3: Repaint with pokadots (vsyrjala)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61152


Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: stable@vger.kernel.org
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 210561ff

drivers/gpu/drm/i915/intel_display.c

+26 −15
Original line number Diff line number Diff line
@@ -2001,18 +2001,29 @@ void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) 


/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel

 * is assumed to be a power-of-two. */

unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,

					       unsigned int bpp,

unsigned long intel_gen4_compute_page_offset(int *x, int *y,

					     unsigned int tiling_mode,

					     unsigned int cpp,

					     unsigned int pitch)

{

	int tile_rows, tiles;

	if (tiling_mode != I915_TILING_NONE) {

		unsigned int tile_rows, tiles;



		tile_rows = *y / 8;

		*y %= 8;

	tiles = *x / (512/bpp);

	*x %= 512/bpp;



		tiles = *x / (512/cpp);

		*x %= 512/cpp;



		return tile_rows * pitch * 8 + tiles * 4096;

	} else {

		unsigned int offset;



		offset = *y * pitch + *x * cpp;

		*y = 0;

		*x = (offset & 4095) / cpp;

		return offset & -4096;

	}

}



static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
@@ -2089,7 +2100,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, 


	if (INTEL_INFO(dev)->gen >= 4) {

		intel_crtc->dspaddr_offset =

			intel_gen4_compute_offset_xtiled(&x, &y,

			intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,

						       fb->bits_per_pixel / 8,

						       fb->pitches[0]);

		linear_offset -= intel_crtc->dspaddr_offset;
@@ -2182,7 +2193,7 @@ static int ironlake_update_plane(struct drm_crtc *crtc, 


	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);

	intel_crtc->dspaddr_offset =

		intel_gen4_compute_offset_xtiled(&x, &y,

		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,

					       fb->bits_per_pixel / 8,

					       fb->pitches[0]);

	linear_offset -= intel_crtc->dspaddr_offset;

drivers/gpu/drm/i915/intel_drv.h

+4 −3
Original line number Diff line number Diff line
@@ -649,7 +649,8 @@ extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, 
extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,

			 struct drm_display_mode *mode);



extern unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,

extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,

						    unsigned int tiling_mode,

						    unsigned int bpp,

						    unsigned int pitch);

drivers/gpu/drm/i915/intel_sprite.c

+4 −4
Original line number Diff line number Diff line
@@ -122,7 +122,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, 


	linear_offset = y * fb->pitches[0] + x * pixel_size;

	sprsurf_offset =

		intel_gen4_compute_offset_xtiled(&x, &y,

		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,

					       pixel_size, fb->pitches[0]);

	linear_offset -= sprsurf_offset;
@@ -295,7 +295,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, 


	linear_offset = y * fb->pitches[0] + x * pixel_size;

	dvssurf_offset =

		intel_gen4_compute_offset_xtiled(&x, &y,

		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,

					       pixel_size, fb->pitches[0]);

	linear_offset -= dvssurf_offset;