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Commit bbeeda27 authored by Ido Schimmel's avatar Ido Schimmel Committed by David S. Miller
Browse files

mlxsw: reg: Use correct offset in field definiton 



The rx_lane, tx_lane and module fields in the PMLP register don't have
an additional offset besides the base one (0x04), so set it to 0x00.

Fixes: 4ec14b76 ("mlxsw: Add interface to access registers and process events")
Signed-off-by: default avatarIdo Schimmel <idosch@mellanox.com>
Signed-off-by: default avatarJiri Pirko <jiri@mellanox.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 3f47f867

drivers/net/ethernet/mellanox/mlxsw/reg.h

+3 −3
Original line number Diff line number Diff line
@@ -1787,20 +1787,20 @@ MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 
 * Module number.

 * Access: RW

 */

MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0, false);

MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);



/* reg_pmlp_tx_lane

 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.

 * Access: RW

 */

MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 16, false);

MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);



/* reg_pmlp_rx_lane

 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is

 * equal to Tx lane.

 * Access: RW

 */

MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 24, false);

MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);



static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)

{