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Commit bbd6c47e authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Reorder submitting the requests to ELSP 



Just rearrange the code to reduce churn in the next patch.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20160909131201.16673-5-chris@chris-wilson.co.uk
parent 8b38b3a1

drivers/gpu/drm/i915/intel_lrc.c

+38 −38
Original line number Original line Diff line number Diff line
@@ -328,32 +328,18 @@ uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx, 
	return ctx->engine[engine->id].lrc_desc;

	return ctx->engine[engine->id].lrc_desc;

}

}





static void execlists_elsp_write(struct drm_i915_gem_request *rq0,

static inline void

				 struct drm_i915_gem_request *rq1)

execlists_context_status_change(struct drm_i915_gem_request *rq,

				unsigned long status)

{

{

	struct intel_engine_cs *engine = rq0->engine;

	/*

	struct drm_i915_private *dev_priv = rq0->i915;

	 * Only used when GVT-g is enabled now. When GVT-g is disabled,

	u32 __iomem *elsp =

	 * The compiler should eliminate this function as dead-code.

		dev_priv->regs + i915_mmio_reg_offset(RING_ELSP(engine));

	 */

	u64 desc[2];

	if (!IS_ENABLED(CONFIG_DRM_I915_GVT))



		return;

	if (rq1) {

		desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->engine);

		rq1->elsp_submitted++;

	} else {

		desc[1] = 0;

	}



	desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->engine);

	rq0->elsp_submitted++;



	/* You must always write both descriptors in the order below. */

	writel(upper_32_bits(desc[1]), elsp);

	writel(lower_32_bits(desc[1]), elsp);





	writel(upper_32_bits(desc[0]), elsp);

	atomic_notifier_call_chain(&rq->ctx->status_notifier, status, rq);

	/* The context is automatically loaded after the following */

	writel(lower_32_bits(desc[0]), elsp);

}

}





static void

static void
@@ -382,6 +368,34 @@ static void execlists_update_context(struct drm_i915_gem_request *rq) 
		execlists_update_context_pdps(ppgtt, reg_state);

		execlists_update_context_pdps(ppgtt, reg_state);

}

}





static void execlists_elsp_write(struct drm_i915_gem_request *rq0,

				 struct drm_i915_gem_request *rq1)

{

	struct intel_engine_cs *engine = rq0->engine;

	struct drm_i915_private *dev_priv = rq0->i915;

	u32 __iomem *elsp =

		dev_priv->regs + i915_mmio_reg_offset(RING_ELSP(engine));

	u64 desc[2];



	if (rq1) {

		desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->engine);

		rq1->elsp_submitted++;

	} else {

		desc[1] = 0;

	}



	desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->engine);

	rq0->elsp_submitted++;



	/* You must always write both descriptors in the order below. */

	writel(upper_32_bits(desc[1]), elsp);

	writel(lower_32_bits(desc[1]), elsp);



	writel(upper_32_bits(desc[0]), elsp);

	/* The context is automatically loaded after the following */

	writel(lower_32_bits(desc[0]), elsp);

}



static void execlists_elsp_submit_contexts(struct drm_i915_gem_request *rq0,

static void execlists_elsp_submit_contexts(struct drm_i915_gem_request *rq0,

					   struct drm_i915_gem_request *rq1)

					   struct drm_i915_gem_request *rq1)

{

{
@@ -402,20 +416,6 @@ static void execlists_elsp_submit_contexts(struct drm_i915_gem_request *rq0, 
	spin_unlock_irq(&dev_priv->uncore.lock);

	spin_unlock_irq(&dev_priv->uncore.lock);

}

}





static inline void execlists_context_status_change(

		struct drm_i915_gem_request *rq,

		unsigned long status)

{

	/*

	 * Only used when GVT-g is enabled now. When GVT-g is disabled,

	 * The compiler should eliminate this function as dead-code.

	 */

	if (!IS_ENABLED(CONFIG_DRM_I915_GVT))

		return;



	atomic_notifier_call_chain(&rq->ctx->status_notifier, status, rq);

}



static void execlists_unqueue(struct intel_engine_cs *engine)

static void execlists_unqueue(struct intel_engine_cs *engine)

{

{

	struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;

	struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;