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Commit bb757a7e authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-intel-fixes' of... 

Merge branch 'drm-intel-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/drm-intel into drm-fixes

* 'drm-intel-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/drm-intel:
  drm/i915: do not enable RC6p on Sandy Bridge
  drm/i915: gen7: Disable the RHWO optimization as it can cause GPU hangs.
  drm/i915: gen7: work around a system hang on IVB
  drm/i915: gen7: Implement an L3 caching workaround.
  drm/i915: gen7: implement rczunit workaround
parents 53ef299f 1c8ecf80

drivers/gpu/drm/i915/i915_reg.h

+15 −0
Original line number Diff line number Diff line
@@ -3028,6 +3028,20 @@ 
#define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)

#define  DISP_FBC_WM_DIS		(1<<15)



/* GEN7 chicken */

#define GEN7_COMMON_SLICE_CHICKEN1		0x7010

# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))



#define GEN7_L3CNTLREG1				0xB01C

#define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C



#define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030

#define  GEN7_WA_L3_CHICKEN_MODE				0x20000000



/* WaCatErrorRejectionIssue */

#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030

#define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)



/* PCH */



/* south display engine interrupt */
@@ -3618,6 +3632,7 @@ 
#define    GT_FIFO_NUM_RESERVED_ENTRIES		20



#define GEN6_UCGCTL2				0x9404

# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)

# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)

# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)

drivers/gpu/drm/i915/intel_display.c

+22 −2
Original line number Diff line number Diff line
@@ -8184,8 +8184,8 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv) 
	I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */



	if (intel_enable_rc6(dev_priv->dev))

		rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |

			GEN6_RC_CTL_RC6_ENABLE;

		rc6_mask = GEN6_RC_CTL_RC6_ENABLE |

			(IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_RC6p_ENABLE : 0;



	I915_WRITE(GEN6_RC_CONTROL,

		   rc6_mask |
@@ -8463,12 +8463,32 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(WM2_LP_ILK, 0);

	I915_WRITE(WM1_LP_ILK, 0);



	/* According to the spec, bit 13 (RCZUNIT) must be set on IVB.

	 * This implements the WaDisableRCZUnitClockGating workaround.

	 */

	I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);



	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);



	I915_WRITE(IVB_CHICKEN3,

		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |

		   CHICKEN3_DGMG_DONE_FIX_DISABLE);



	/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */

	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,

		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);



	/* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */

	I915_WRITE(GEN7_L3CNTLREG1,

			GEN7_WA_FOR_GEN7_L3_CONTROL);

	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,

			GEN7_WA_L3_CHICKEN_MODE);



	/* This is required by WaCatErrorRejectionIssue */

	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,

			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |

			GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);



	for_each_pipe(pipe) {

		I915_WRITE(DSPCNTR(pipe),

			   I915_READ(DSPCNTR(pipe)) |