Commit bb66c512 authored Sep 10, 2009 by Zhao Yakui Committed by Eric Anholt Sep 10, 2009

drm/i915: Write zero to DPLL_MD Reg for non-SDVO output

When the output device is LVDS, maybe the pixel clock of adjusted_mode will be
less than that in mode. In such case it will set the incorrect multipler factor
in DPLL_MD register.
So the dpll_md_reg will be reset when the output type is non-SDVO

https://bugs.freedesktop.org/show_bug.cgi?id=22761



Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewd-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Eric Anholt <eric@anholt.net>

parent e270846f

drivers/gpu/drm/i915/intel_display.c

+5 −2

Original line number	Diff line number	Diff line
		@@ -2652,9 +2652,12 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
		udelay(150);

		if (IS_I965G(dev) && !IS_IGDNG(dev)) {
		if (is_sdvo) {
		sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
		I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) \|
		((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
		} else
		I915_WRITE(dpll_md_reg, 0);
		} else {
		/* write it again -- the BIOS does, after all */
		I915_WRITE(dpll_reg, dpll);