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Commit b943d0b9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux 

Pull drm fixes from Dave Airlie:
 "Summary:

  - Misc amdgpu/radeon fixes
  - VC4 build fix
  - vmwgfx fix
  - misc rockchip fixes

  The etnaviv guys had an API feature they wanted in their first
  release, so I've merged that with their fixes"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (41 commits)
  drm/vmwgfx: respect 'nomodeset'
  drm/amdgpu: only move pt bos in LRU list on success
  drm/radeon: fix DP audio support for APU with DCE4.1 display engine
  drm/radeon: Add a common function for DFS handling
  drm/radeon: cleaned up VCO output settings for DP audio
  drm/amd/powerplay: Update SMU firmware loading for Stoney
  drm/etnaviv: call correct function when trying to vmap a DMABUF
  drm/etnaviv: rename etnaviv_gem_vaddr to etnaviv_gem_vmap
  drm/etnaviv: fix get pages error path in etnaviv_gem_vaddr
  drm/etnaviv: fix memory leak in IOMMU init path
  drm/etnaviv: add further minor features and varyings count
  drm/etnaviv: add helper for comparing model/revision IDs
  drm/etnaviv: add helper to extract bitfields
  drm/etnaviv: use defined constants for the chip model
  drm/etnaviv: update common and state_hi xml.h files
  drm/etnaviv: ignore VG GPUs with FE2.0
  drm/amdgpu: don't init fbdev if we don't have any connectors
  drm/radeon: only init fbdev if we have connectors
  drm/radeon: Ensure radeon bo is unreserved in radeon_gem_va_ioctl
  drm/etnaviv: fix failure path if model is zero
  ...
parents 704bb813 d8b8eb82

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+22 −22
Original line number Diff line number Diff line
@@ -2278,60 +2278,60 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 
#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))



#define amdgpu_dpm_get_temperature(adev) \

	(adev)->pp_enabled ?						\

	((adev)->pp_enabled ?						\

	      (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \

	      (adev)->pm.funcs->get_temperature((adev))

	      (adev)->pm.funcs->get_temperature((adev)))



#define amdgpu_dpm_set_fan_control_mode(adev, m) \

	(adev)->pp_enabled ?						\

	((adev)->pp_enabled ?						\

	      (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \

	      (adev)->pm.funcs->set_fan_control_mode((adev), (m))

	      (adev)->pm.funcs->set_fan_control_mode((adev), (m)))



#define amdgpu_dpm_get_fan_control_mode(adev) \

	(adev)->pp_enabled ?						\

	((adev)->pp_enabled ?						\

	      (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \

	      (adev)->pm.funcs->get_fan_control_mode((adev))

	      (adev)->pm.funcs->get_fan_control_mode((adev)))



#define amdgpu_dpm_set_fan_speed_percent(adev, s) \

	(adev)->pp_enabled ?						\

	((adev)->pp_enabled ?						\

	      (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \

	      (adev)->pm.funcs->set_fan_speed_percent((adev), (s))

	      (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))



#define amdgpu_dpm_get_fan_speed_percent(adev, s) \

	(adev)->pp_enabled ?						\

	((adev)->pp_enabled ?						\

	      (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \

	      (adev)->pm.funcs->get_fan_speed_percent((adev), (s))

	      (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))



#define amdgpu_dpm_get_sclk(adev, l) \

	(adev)->pp_enabled ?						\

	((adev)->pp_enabled ?						\

	      (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \

		(adev)->pm.funcs->get_sclk((adev), (l))

		(adev)->pm.funcs->get_sclk((adev), (l)))



#define amdgpu_dpm_get_mclk(adev, l)  \

	(adev)->pp_enabled ?						\

	((adev)->pp_enabled ?						\

	      (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \

	      (adev)->pm.funcs->get_mclk((adev), (l))

	      (adev)->pm.funcs->get_mclk((adev), (l)))





#define amdgpu_dpm_force_performance_level(adev, l) \

	(adev)->pp_enabled ?						\

	((adev)->pp_enabled ?						\

	      (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \

	      (adev)->pm.funcs->force_performance_level((adev), (l))

	      (adev)->pm.funcs->force_performance_level((adev), (l)))



#define amdgpu_dpm_powergate_uvd(adev, g) \

	(adev)->pp_enabled ?						\

	((adev)->pp_enabled ?						\

	      (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \

	      (adev)->pm.funcs->powergate_uvd((adev), (g))

	      (adev)->pm.funcs->powergate_uvd((adev), (g)))



#define amdgpu_dpm_powergate_vce(adev, g) \

	(adev)->pp_enabled ?						\

	((adev)->pp_enabled ?						\

	      (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \

	      (adev)->pm.funcs->powergate_vce((adev), (g))

	      (adev)->pm.funcs->powergate_vce((adev), (g)))



#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \

	(adev)->pp_enabled ?						\

	((adev)->pp_enabled ?						\

	      (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \

	      (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))

	      (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))



#define amdgpu_dpm_get_current_power_state(adev) \

	(adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+2 −2
Original line number Diff line number Diff line
@@ -478,9 +478,9 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bo 
	struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;

	unsigned i;



	if (!error) {

		amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm);



	if (!error) {

		/* Sort the buffer list from the smallest to largest buffer,

		 * which affects the order of buffers in the LRU list.

		 * This assures that the smallest buffers are added first

drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c

+4 −0
Original line number Diff line number Diff line
@@ -333,6 +333,10 @@ int amdgpu_fbdev_init(struct amdgpu_device *adev) 
	if (!adev->mode_info.mode_config_initialized)

		return 0;



	/* don't init fbdev if there are no connectors */

	if (list_empty(&adev->ddev->mode_config.connector_list))

		return 0;



	/* select 8 bpp console on low vram cards */

	if (adev->mc.real_vram_size <= (32*1024*1024))

		bpp_sel = 8;

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

+2 −1
Original line number Diff line number Diff line
@@ -399,7 +399,8 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 
		}

		if (fpfn > bo->placements[i].fpfn)

			bo->placements[i].fpfn = fpfn;

		if (lpfn && lpfn < bo->placements[i].lpfn)

		if (!bo->placements[i].lpfn ||

		    (lpfn && lpfn < bo->placements[i].lpfn))

			bo->placements[i].lpfn = lpfn;

		bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c

+18 −7
Original line number Diff line number Diff line
@@ -101,10 +101,21 @@ static int amdgpu_pp_early_init(void *handle) 
	switch (adev->asic_type) {

	case CHIP_TONGA:

	case CHIP_FIJI:

		adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true;

		break;

	case CHIP_CARRIZO:

	case CHIP_STONEY:

		adev->pp_enabled = (amdgpu_powerplay > 0) ? true : false;

		break;

	/* These chips don't have powerplay implemenations */

	case CHIP_BONAIRE:

	case CHIP_HAWAII:

	case CHIP_KABINI:

	case CHIP_MULLINS:

	case CHIP_KAVERI:

	case CHIP_TOPAZ:

	default:

			adev->pp_enabled = (amdgpu_powerplay > 0) ? true : false;

		adev->pp_enabled = false;

		break;

	}

#else