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Commit b8f15e71 authored by Michael Turquette's avatar Michael Turquette
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Merge commit 'fe5fa8fbd4d47f40a45fa29ee1abdb10cb061ec2' into clk-next

parents 4ef76753 fcd5ac1a
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@@ -208,3 +208,8 @@ These clock IDs are defined in:
    ch3_unused	lcpll_ports	4	BCM_NS2_LCPLL_PORTS_CH3_UNUSED
    ch4_unused	lcpll_ports	5	BCM_NS2_LCPLL_PORTS_CH4_UNUSED
    ch5_unused	lcpll_ports	6	BCM_NS2_LCPLL_PORTS_CH5_UNUSED

BCM63138
--------
PLL and leaf clock compatible strings for BCM63138 are:
    "brcm,bcm63138-armpll"
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CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier

Required properties:

- compatible:		"cirrus,cs2000-cp"
- reg:			The chip select number on the I2C bus
- clocks:		common clock binding for CLK_IN, XTI/REF_CLK
- clock-names:		CLK_IN : clk_in, XTI/REF_CLK : ref_clk
- #clock-cells:		must be <0>

Example:

&i2c2 {
	...
	cs2000: clk_multiplier@4f {
		#clock-cells = <0>;
		compatible = "cirrus,cs2000-cp";
		reg = <0x4f>;
		clocks = <&rcar_sound 0>, <&x12_clk>;
		clock-names = "clk_in", "ref_clk";
	};
};
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@@ -13,6 +13,7 @@ Required properties :
			"qcom,gcc-msm8974"
			"qcom,gcc-msm8974pro"
			"qcom,gcc-msm8974pro-ac"
			"qcom,gcc-msm8996"

- reg : shall contain base register location and length
- #clock-cells : shall contain 1
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@@ -9,6 +9,7 @@ Required properties :
			"qcom,mmcc-msm8660"
			"qcom,mmcc-msm8960"
			"qcom,mmcc-msm8974"
			"qcom,mmcc-msm8996"

- reg : shall contain base register location and length
- #clock-cells : shall contain 1
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@@ -20,6 +20,10 @@ Required Properties:
    clocks must be specified.  For clocks with multiple parents, invalid
    settings must be specified as "<0>".
  - #clock-cells: Must be 0


Optional Properties:

  - clock-output-names: The name of the clock as a free-form string


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