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Commit b8cab706 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux 

Pull drm fixes from Dave Airlie:
 "Mainly Intel regression fixes and quirks, along with a simple one
  liner to fix rendernodes ioctl access (off by default, but testers
  want to test it)"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
  drm: allow DRM_IOCTL_VERSION on render-nodes
  drm/i915: Fix the PPT fdi lane bifurcate state handling on ivb
  drm/i915: No LVDS hardware on Intel D410PT and D425KT
  drm/i915/dp: workaround BIOS eDP bpp clamping issue
  drm/i915: Add HSW CRT output readout support
  drm/i915: Add support for pipe_bpp readout
parents 182b4fd9 3d3b78c0

drivers/gpu/drm/drm_drv.c

+1 −1
Original line number Diff line number Diff line
@@ -61,7 +61,7 @@ static int drm_version(struct drm_device *dev, void *data, 


/** Ioctl table */

static const struct drm_ioctl_desc drm_ioctls[] = {

	DRM_IOCTL_DEF(DRM_IOCTL_VERSION, drm_version, DRM_UNLOCKED),

	DRM_IOCTL_DEF(DRM_IOCTL_VERSION, drm_version, DRM_UNLOCKED|DRM_RENDER_ALLOW),

	DRM_IOCTL_DEF(DRM_IOCTL_GET_UNIQUE, drm_getunique, 0),

	DRM_IOCTL_DEF(DRM_IOCTL_GET_MAGIC, drm_getmagic, 0),

	DRM_IOCTL_DEF(DRM_IOCTL_IRQ_BUSID, drm_irq_by_busid, DRM_MASTER|DRM_ROOT_ONLY),

drivers/gpu/drm/i915/intel_crt.c

+26 −4
Original line number Diff line number Diff line
@@ -83,8 +83,7 @@ static bool intel_crt_get_hw_state(struct intel_encoder *encoder, 
	return true;

}



static void intel_crt_get_config(struct intel_encoder *encoder,

				 struct intel_crtc_config *pipe_config)

static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)

{

	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;

	struct intel_crt *crt = intel_encoder_to_crt(encoder);
@@ -102,7 +101,27 @@ static void intel_crt_get_config(struct intel_encoder *encoder, 
	else

		flags |= DRM_MODE_FLAG_NVSYNC;



	pipe_config->adjusted_mode.flags |= flags;

	return flags;

}



static void intel_crt_get_config(struct intel_encoder *encoder,

				 struct intel_crtc_config *pipe_config)

{

	struct drm_device *dev = encoder->base.dev;



	pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);

}



static void hsw_crt_get_config(struct intel_encoder *encoder,

			       struct intel_crtc_config *pipe_config)

{

	intel_ddi_get_config(encoder, pipe_config);



	pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |

					      DRM_MODE_FLAG_NHSYNC |

					      DRM_MODE_FLAG_PVSYNC |

					      DRM_MODE_FLAG_NVSYNC);

	pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);

}



/* Note: The caller is required to filter out dpms modes not supported by the
@@ -799,6 +818,9 @@ void intel_crt_init(struct drm_device *dev) 
	crt->base.mode_set = intel_crt_mode_set;

	crt->base.disable = intel_disable_crt;

	crt->base.enable = intel_enable_crt;

	if (IS_HASWELL(dev))

		crt->base.get_config = hsw_crt_get_config;

	else

		crt->base.get_config = intel_crt_get_config;

	if (I915_HAS_HOTPLUG(dev))

		crt->base.hpd_pin = HPD_CRT;

drivers/gpu/drm/i915/intel_ddi.c

+19 −2
Original line number Diff line number Diff line
@@ -1249,7 +1249,7 @@ static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder) 
		intel_dp_check_link_status(intel_dp);

}



static void intel_ddi_get_config(struct intel_encoder *encoder,

void intel_ddi_get_config(struct intel_encoder *encoder,

			  struct intel_crtc_config *pipe_config)

{

	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
@@ -1268,6 +1268,23 @@ static void intel_ddi_get_config(struct intel_encoder *encoder, 
		flags |= DRM_MODE_FLAG_NVSYNC;



	pipe_config->adjusted_mode.flags |= flags;



	switch (temp & TRANS_DDI_BPC_MASK) {

	case TRANS_DDI_BPC_6:

		pipe_config->pipe_bpp = 18;

		break;

	case TRANS_DDI_BPC_8:

		pipe_config->pipe_bpp = 24;

		break;

	case TRANS_DDI_BPC_10:

		pipe_config->pipe_bpp = 30;

		break;

	case TRANS_DDI_BPC_12:

		pipe_config->pipe_bpp = 36;

		break;

	default:

		break;

	}

}



static void intel_ddi_destroy(struct drm_encoder *encoder)

drivers/gpu/drm/i915/intel_display.c

+84 −47
Original line number Diff line number Diff line
@@ -2327,9 +2327,10 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc) 
			   FDI_FE_ERRC_ENABLE);

}



static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)

static bool pipe_has_enabled_pch(struct intel_crtc *crtc)

{

	return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;

	return crtc->base.enabled && crtc->active &&

		crtc->config.has_pch_encoder;

}



static void ivb_modeset_global_resources(struct drm_device *dev)
@@ -2979,6 +2980,48 @@ static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, 
		   I915_READ(VSYNCSHIFT(cpu_transcoder)));

}



static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	uint32_t temp;



	temp = I915_READ(SOUTH_CHICKEN1);

	if (temp & FDI_BC_BIFURCATION_SELECT)

		return;



	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);

	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);



	temp |= FDI_BC_BIFURCATION_SELECT;

	DRM_DEBUG_KMS("enabling fdi C rx\n");

	I915_WRITE(SOUTH_CHICKEN1, temp);

	POSTING_READ(SOUTH_CHICKEN1);

}



static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)

{

	struct drm_device *dev = intel_crtc->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;



	switch (intel_crtc->pipe) {

	case PIPE_A:

		break;

	case PIPE_B:

		if (intel_crtc->config.fdi_lanes > 2)

			WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);

		else

			cpt_enable_fdi_bc_bifurcation(dev);



		break;

	case PIPE_C:

		cpt_enable_fdi_bc_bifurcation(dev);



		break;

	default:

		BUG();

	}

}



/*

 * Enable PCH resources required for PCH ports:

 *   - PCH PLLs
@@ -2997,6 +3040,9 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) 


	assert_pch_transcoder_disabled(dev_priv, pipe);



	if (IS_IVYBRIDGE(dev))

		ivybridge_update_fdi_bc_bifurcation(intel_crtc);



	/* Write the TU size bits before fdi link training, so that error

	 * detection works. */

	I915_WRITE(FDI_RX_TUSIZE1(pipe),
@@ -4983,6 +5029,22 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 
	if (!(tmp & PIPECONF_ENABLE))

		return false;



	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {

		switch (tmp & PIPECONF_BPC_MASK) {

		case PIPECONF_6BPC:

			pipe_config->pipe_bpp = 18;

			break;

		case PIPECONF_8BPC:

			pipe_config->pipe_bpp = 24;

			break;

		case PIPECONF_10BPC:

			pipe_config->pipe_bpp = 30;

			break;

		default:

			break;

		}

	}



	intel_get_pipe_timings(crtc, pipe_config);



	i9xx_get_pfit_config(crtc, pipe_config);
@@ -5576,48 +5638,6 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc, 
	return true;

}



static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	uint32_t temp;



	temp = I915_READ(SOUTH_CHICKEN1);

	if (temp & FDI_BC_BIFURCATION_SELECT)

		return;



	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);

	WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);



	temp |= FDI_BC_BIFURCATION_SELECT;

	DRM_DEBUG_KMS("enabling fdi C rx\n");

	I915_WRITE(SOUTH_CHICKEN1, temp);

	POSTING_READ(SOUTH_CHICKEN1);

}



static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)

{

	struct drm_device *dev = intel_crtc->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;



	switch (intel_crtc->pipe) {

	case PIPE_A:

		break;

	case PIPE_B:

		if (intel_crtc->config.fdi_lanes > 2)

			WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);

		else

			cpt_enable_fdi_bc_bifurcation(dev);



		break;

	case PIPE_C:

		cpt_enable_fdi_bc_bifurcation(dev);



		break;

	default:

		BUG();

	}

}



int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)

{

	/*
@@ -5811,9 +5831,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
					     &intel_crtc->config.fdi_m_n);

	}



	if (IS_IVYBRIDGE(dev))

		ivybridge_update_fdi_bc_bifurcation(intel_crtc);



	ironlake_set_pipeconf(crtc);



	/* Set up the display plane register */
@@ -5881,6 +5898,23 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc, 
	if (!(tmp & PIPECONF_ENABLE))

		return false;



	switch (tmp & PIPECONF_BPC_MASK) {

	case PIPECONF_6BPC:

		pipe_config->pipe_bpp = 18;

		break;

	case PIPECONF_8BPC:

		pipe_config->pipe_bpp = 24;

		break;

	case PIPECONF_10BPC:

		pipe_config->pipe_bpp = 30;

		break;

	case PIPECONF_12BPC:

		pipe_config->pipe_bpp = 36;

		break;

	default:

		break;

	}



	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {

		struct intel_shared_dpll *pll;
@@ -8612,6 +8646,9 @@ intel_pipe_config_compare(struct drm_device *dev, 
	PIPE_CONF_CHECK_X(dpll_hw_state.fp0);

	PIPE_CONF_CHECK_X(dpll_hw_state.fp1);



	if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)

		PIPE_CONF_CHECK_I(pipe_bpp);



#undef PIPE_CONF_CHECK_X

#undef PIPE_CONF_CHECK_I

#undef PIPE_CONF_CHECK_FLAGS

drivers/gpu/drm/i915/intel_dp.c

+20 −0
Original line number Diff line number Diff line
@@ -1401,6 +1401,26 @@ static void intel_dp_get_config(struct intel_encoder *encoder, 
		else

			pipe_config->port_clock = 270000;

	}



	if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&

	    pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {

		/*

		 * This is a big fat ugly hack.

		 *

		 * Some machines in UEFI boot mode provide us a VBT that has 18

		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons

		 * unknown we fail to light up. Yet the same BIOS boots up with

		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as

		 * max, not what it tells us to use.

		 *

		 * Note: This will still be broken if the eDP panel is not lit

		 * up by the BIOS, and thus we can't get the mode at module

		 * load.

		 */

		DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",

			      pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);

		dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;

	}

}



static bool is_edp_psr(struct intel_dp *intel_dp)