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Commit b824efae authored by Tony Lindgren's avatar Tony Lindgren Committed by Russell King
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[ARM] 3426/1: ARM: OMAP: 1/8 Update clock framework 



Patch from Tony Lindgren

Update OMAP clock framework from linux-omap tree.
The highlights of the patch are:

- Add support for omap730 clocks by Andrzej Zaborowski
- Fix compile warnings by Dirk Behme
- Add support for using dev id by Tony Lindgren and Komal Shah
- Move memory timings and PRCM into separate files by Tony Lindgren

Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 3267c077

arch/arm/mach-omap1/clock.c

+7 −2
Original line number Diff line number Diff line
@@ -687,6 +687,11 @@ int __init omap1_clk_init(void) 
			clk_register(*clkp);

			continue;

		}



		if (((*clkp)->flags &CLOCK_IN_OMAP310) && cpu_is_omap310()) {

			clk_register(*clkp);

			continue;

		}

	}



	info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
@@ -784,7 +789,7 @@ int __init omap1_clk_init(void) 
	clk_enable(&armxor_ck.clk);

	clk_enable(&armtim_ck.clk); /* This should be done by timer code */



	if (cpu_is_omap1510())

	if (cpu_is_omap15xx())

		clk_enable(&arm_gpio_ck);



	return 0;

arch/arm/mach-omap1/clock.h

+59 −32
Original line number Diff line number Diff line
@@ -151,7 +151,7 @@ static struct clk ck_ref = { 
	.name		= "ck_ref",

	.rate		= 12000000,

	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |

			  ALWAYS_ENABLED,

			  CLOCK_IN_OMAP310 | ALWAYS_ENABLED,

	.enable		= &omap1_clk_enable_generic,

	.disable	= &omap1_clk_disable_generic,

};
@@ -160,7 +160,7 @@ static struct clk ck_dpll1 = { 
	.name		= "ck_dpll1",

	.parent		= &ck_ref,

	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |

			  RATE_PROPAGATES | ALWAYS_ENABLED,

			  CLOCK_IN_OMAP310 | RATE_PROPAGATES | ALWAYS_ENABLED,

	.enable		= &omap1_clk_enable_generic,

	.disable	= &omap1_clk_disable_generic,

};
@@ -183,7 +183,8 @@ static struct clk arm_ck = { 
	.name		= "arm_ck",

	.parent		= &ck_dpll1,

	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |

			  RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED,

			  CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES |

			  ALWAYS_ENABLED,

	.rate_offset	= CKCTL_ARMDIV_OFFSET,

	.recalc		= &omap1_ckctl_recalc,

	.enable		= &omap1_clk_enable_generic,
@@ -195,7 +196,8 @@ static struct arm_idlect1_clk armper_ck = { 
		.name		= "armper_ck",

		.parent		= &ck_dpll1,

		.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |

				  RATE_CKCTL | CLOCK_IDLE_CONTROL,

				  CLOCK_IN_OMAP310 | RATE_CKCTL |

				  CLOCK_IDLE_CONTROL,

		.enable_reg	= (void __iomem *)ARM_IDLECT2,

		.enable_bit	= EN_PERCK,

		.rate_offset	= CKCTL_PERDIV_OFFSET,
@@ -209,7 +211,7 @@ static struct arm_idlect1_clk armper_ck = { 
static struct clk arm_gpio_ck = {

	.name		= "arm_gpio_ck",

	.parent		= &ck_dpll1,

	.flags		= CLOCK_IN_OMAP1510,

	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,

	.enable_reg	= (void __iomem *)ARM_IDLECT2,

	.enable_bit	= EN_GPIOCK,

	.recalc		= &followparent_recalc,
@@ -222,7 +224,7 @@ static struct arm_idlect1_clk armxor_ck = { 
		.name		= "armxor_ck",

		.parent		= &ck_ref,

		.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |

				  CLOCK_IDLE_CONTROL,

				  CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,

		.enable_reg	= (void __iomem *)ARM_IDLECT2,

		.enable_bit	= EN_XORPCK,

		.recalc		= &followparent_recalc,
@@ -237,7 +239,7 @@ static struct arm_idlect1_clk armtim_ck = { 
		.name		= "armtim_ck",

		.parent		= &ck_ref,

		.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |

				  CLOCK_IDLE_CONTROL,

				  CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,

		.enable_reg	= (void __iomem *)ARM_IDLECT2,

		.enable_bit	= EN_TIMCK,

		.recalc		= &followparent_recalc,
@@ -252,7 +254,7 @@ static struct arm_idlect1_clk armwdt_ck = { 
		.name		= "armwdt_ck",

		.parent		= &ck_ref,

		.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |

				  CLOCK_IDLE_CONTROL,

				  CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,

		.enable_reg	= (void __iomem *)ARM_IDLECT2,

		.enable_bit	= EN_WDTCK,

		.recalc		= &omap1_watchdog_recalc,
@@ -344,9 +346,9 @@ static struct arm_idlect1_clk tc_ck = { 
		.name		= "tc_ck",

		.parent		= &ck_dpll1,

		.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |

				  CLOCK_IN_OMAP730 | RATE_CKCTL |

				  RATE_PROPAGATES | ALWAYS_ENABLED |

				  CLOCK_IDLE_CONTROL,

				  CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |

				  RATE_CKCTL | RATE_PROPAGATES |

				  ALWAYS_ENABLED | CLOCK_IDLE_CONTROL,

		.rate_offset	= CKCTL_TCDIV_OFFSET,

		.recalc		= &omap1_ckctl_recalc,

		.enable		= &omap1_clk_enable_generic,
@@ -358,7 +360,8 @@ static struct arm_idlect1_clk tc_ck = { 
static struct clk arminth_ck1510 = {

	.name		= "arminth_ck",

	.parent		= &tc_ck.clk,

	.flags		= CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,

	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |

			  ALWAYS_ENABLED,

	.recalc		= &followparent_recalc,

	/* Note: On 1510 the frequency follows TC_CK

	 *
@@ -372,7 +375,8 @@ static struct clk tipb_ck = { 
	/* No-idle controlled by "tc_ck" */

	.name		= "tibp_ck",

	.parent		= &tc_ck.clk,

	.flags		= CLOCK_IN_OMAP1510 | ALWAYS_ENABLED,

	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |

			  ALWAYS_ENABLED,

	.recalc		= &followparent_recalc,

	.enable		= &omap1_clk_enable_generic,

	.disable	= &omap1_clk_disable_generic,
@@ -417,7 +421,7 @@ static struct clk dma_ck = { 
	.name		= "dma_ck",

	.parent		= &tc_ck.clk,

	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |

			  ALWAYS_ENABLED,

			  CLOCK_IN_OMAP310 | ALWAYS_ENABLED,

	.recalc		= &followparent_recalc,

	.enable		= &omap1_clk_enable_generic,

	.disable	= &omap1_clk_disable_generic,
@@ -437,7 +441,7 @@ static struct arm_idlect1_clk api_ck = { 
		.name		= "api_ck",

		.parent		= &tc_ck.clk,

		.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |

				  CLOCK_IDLE_CONTROL,

				  CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,

		.enable_reg	= (void __iomem *)ARM_IDLECT2,

		.enable_bit	= EN_APICK,

		.recalc		= &followparent_recalc,
@@ -451,7 +455,8 @@ static struct arm_idlect1_clk lb_ck = { 
	.clk = {

		.name		= "lb_ck",

		.parent		= &tc_ck.clk,

		.flags		= CLOCK_IN_OMAP1510 | CLOCK_IDLE_CONTROL,

		.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |

				  CLOCK_IDLE_CONTROL,

		.enable_reg	= (void __iomem *)ARM_IDLECT2,

		.enable_bit	= EN_LBCK,

		.recalc		= &followparent_recalc,
@@ -495,8 +500,8 @@ static struct arm_idlect1_clk lcd_ck_1510 = { 
	.clk = {

		.name		= "lcd_ck",

		.parent		= &ck_dpll1,

		.flags		= CLOCK_IN_OMAP1510 | RATE_CKCTL |

				  CLOCK_IDLE_CONTROL,

		.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |

				  RATE_CKCTL | CLOCK_IDLE_CONTROL,

		.enable_reg	= (void __iomem *)ARM_IDLECT2,

		.enable_bit	= EN_LCDCK,

		.rate_offset	= CKCTL_LCDDIV_OFFSET,
@@ -512,8 +517,9 @@ static struct clk uart1_1510 = { 
	/* Direct from ULPD, no real parent */

	.parent		= &armper_ck.clk,

	.rate		= 12000000,

	.flags		= CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT |

			  ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT,

	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |

			  ENABLE_REG_32BIT | ALWAYS_ENABLED |

			  CLOCK_NO_IDLE_PARENT,

	.enable_reg	= (void __iomem *)MOD_CONF_CTRL_0,

	.enable_bit	= 29,	/* Chooses between 12MHz and 48MHz */

	.set_rate	= &omap1_set_uart_rate,
@@ -544,8 +550,8 @@ static struct clk uart2_ck = { 
	.parent		= &armper_ck.clk,

	.rate		= 12000000,

	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |

			  ENABLE_REG_32BIT | ALWAYS_ENABLED |

			  CLOCK_NO_IDLE_PARENT,

			  CLOCK_IN_OMAP310 | ENABLE_REG_32BIT |

			  ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT,

	.enable_reg	= (void __iomem *)MOD_CONF_CTRL_0,

	.enable_bit	= 30,	/* Chooses between 12MHz and 48MHz */

	.set_rate	= &omap1_set_uart_rate,
@@ -559,8 +565,9 @@ static struct clk uart3_1510 = { 
	/* Direct from ULPD, no real parent */

	.parent		= &armper_ck.clk,

	.rate		= 12000000,

	.flags		= CLOCK_IN_OMAP1510 | ENABLE_REG_32BIT |

			  ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT,

	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |

			  ENABLE_REG_32BIT | ALWAYS_ENABLED |

			  CLOCK_NO_IDLE_PARENT,

	.enable_reg	= (void __iomem *)MOD_CONF_CTRL_0,

	.enable_bit	= 31,	/* Chooses between 12MHz and 48MHz */

	.set_rate	= &omap1_set_uart_rate,
@@ -590,7 +597,7 @@ static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ 
	/* Direct from ULPD, no parent */

	.rate		= 6000000,

	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |

			  RATE_FIXED | ENABLE_REG_32BIT,

			  CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT,

	.enable_reg	= (void __iomem *)ULPD_CLOCK_CTRL,

	.enable_bit	= USB_MCLK_EN_BIT,

	.enable		= &omap1_clk_enable_generic,
@@ -601,7 +608,7 @@ static struct clk usb_hhc_ck1510 = { 
	.name		= "usb_hhc_ck",

	/* Direct from ULPD, no parent */

	.rate		= 48000000, /* Actually 2 clocks, 12MHz and 48MHz */

	.flags		= CLOCK_IN_OMAP1510 |

	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |

			  RATE_FIXED | ENABLE_REG_32BIT,

	.enable_reg	= (void __iomem *)MOD_CONF_CTRL_0,

	.enable_bit	= USB_HOST_HHC_UHOST_EN,
@@ -637,7 +644,9 @@ static struct clk mclk_1510 = { 
	.name		= "mclk",

	/* Direct from ULPD, no parent. May be enabled by ext hardware. */

	.rate		= 12000000,

	.flags		= CLOCK_IN_OMAP1510 | RATE_FIXED,

 	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,

 	.enable_reg	= (void __iomem *)SOFT_REQ_REG,

 	.enable_bit	= 6,

	.enable		= &omap1_clk_enable_generic,

	.disable	= &omap1_clk_disable_generic,

};
@@ -659,7 +668,7 @@ static struct clk bclk_1510 = { 
	.name		= "bclk",

	/* Direct from ULPD, no parent. May be enabled by ext hardware. */

	.rate		= 12000000,

	.flags		= CLOCK_IN_OMAP1510 | RATE_FIXED,

	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,

	.enable		= &omap1_clk_enable_generic,

	.disable	= &omap1_clk_disable_generic,

};
@@ -678,12 +687,14 @@ static struct clk bclk_16xx = { 
};



static struct clk mmc1_ck = {

	.name		= "mmc1_ck",

	.name		= "mmc_ck",

	.id		= 1,

	/* Functional clock is direct from ULPD, interface clock is ARMPER */

	.parent		= &armper_ck.clk,

	.rate		= 48000000,

	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |

			  RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,

			  CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT |

			  CLOCK_NO_IDLE_PARENT,

	.enable_reg	= (void __iomem *)MOD_CONF_CTRL_0,

	.enable_bit	= 23,

	.enable		= &omap1_clk_enable_generic,
@@ -691,7 +702,8 @@ static struct clk mmc1_ck = { 
};



static struct clk mmc2_ck = {

	.name		= "mmc2_ck",

	.name		= "mmc_ck",

	.id		= 2,

	/* Functional clock is direct from ULPD, interface clock is ARMPER */

	.parent		= &armper_ck.clk,

	.rate		= 48000000,
@@ -706,7 +718,7 @@ static struct clk mmc2_ck = { 
static struct clk virtual_ck_mpu = {

	.name		= "mpu",

	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |

			  VIRTUAL_CLOCK | ALWAYS_ENABLED,

			  CLOCK_IN_OMAP310 | VIRTUAL_CLOCK | ALWAYS_ENABLED,

	.parent		= &arm_ck, /* Is smarter alias for */

	.recalc		= &followparent_recalc,

	.set_rate	= &omap1_select_table_rate,
@@ -715,6 +727,20 @@ static struct clk virtual_ck_mpu = { 
	.disable	= &omap1_clk_disable_generic,

};



/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK

remains active during MPU idle whenever this is enabled */

static struct clk i2c_fck = {

	.name		= "i2c_fck",

	.id		= 1,

	.flags		= CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |

			  VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT |

			  ALWAYS_ENABLED,

	.parent		= &armxor_ck.clk,

	.recalc		= &followparent_recalc,

	.enable		= &omap1_clk_enable_generic,

	.disable	= &omap1_clk_disable_generic,

};



static struct clk * onchip_clks[] = {

	/* non-ULPD clocks */

	&ck_ref,
@@ -763,6 +789,7 @@ static struct clk * onchip_clks[] = { 
	&mmc2_ck,

	/* Virtual clocks */

	&virtual_ck_mpu,

	&i2c_fck,

};



#endif

arch/arm/mach-omap2/clock.c

+14 −65
Original line number Diff line number Diff line
@@ -28,14 +28,14 @@ 


#include <asm/arch/clock.h>

#include <asm/arch/sram.h>

#include <asm/arch/prcm.h>



#include "prcm-regs.h"

#include "memory.h"

#include "clock.h"



//#define DOWN_VARIABLE_DPLL 1			/* Experimental */



static struct prcm_config *curr_prcm_set;

static struct memory_timings mem_timings;

static u32 curr_perf_level = PRCM_FULL_SPEED;



/*-------------------------------------------------------------------------
@@ -54,11 +54,13 @@ static void omap2_sys_clk_recalc(struct clk * clk) 


static u32 omap2_get_dpll_rate(struct clk * tclk)

{

	int dpll_clk, dpll_mult, dpll_div, amult;

	long long dpll_clk;

	int dpll_mult, dpll_div, amult;



	dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff;	/* 10 bits */

	dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f;	/* 4 bits */

	dpll_clk = (tclk->parent->rate * dpll_mult) / (dpll_div + 1);

	dpll_clk = (long long)tclk->parent->rate * dpll_mult;

	do_div(dpll_clk, dpll_div + 1);

	amult = CM_CLKSEL2_PLL & 0x3;

	dpll_clk *= amult;
@@ -385,75 +387,23 @@ static u32 omap2_dll_force_needed(void) 
		return 0;

}



static void omap2_init_memory_params(u32 force_lock_to_unlock_mode)

{

	unsigned long dll_cnt;

	u32 fast_dll = 0;



	mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */



	/* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.

	 * In the case of 2422, its ok to use CS1 instead of CS0.

	 */



#if 0	/* FIXME: Enable after 24xx cpu detection works */

	ctype = get_cpu_type();

	if (cpu_is_omap2422())

		mem_timings.base_cs = 1;

	else

#endif

		mem_timings.base_cs = 0;



	if (mem_timings.m_type != M_DDR)

		return;



	/* With DDR we need to determine the low frequency DLL value */

	if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))

		mem_timings.dll_mode = M_UNLOCK;

	else

		mem_timings.dll_mode = M_LOCK;



	if (mem_timings.base_cs == 0) {

		fast_dll = SDRC_DLLA_CTRL;

		dll_cnt = SDRC_DLLA_STATUS & 0xff00;

	} else {

		fast_dll = SDRC_DLLB_CTRL;

		dll_cnt = SDRC_DLLB_STATUS & 0xff00;

	}

	if (force_lock_to_unlock_mode) {

		fast_dll &= ~0xff00;

		fast_dll |= dll_cnt;		/* Current lock mode */

	}

	mem_timings.fast_dll_ctrl = fast_dll;



	/* No disruptions, DDR will be offline & C-ABI not followed */

	omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,

			    mem_timings.fast_dll_ctrl,

			    mem_timings.base_cs,

			    force_lock_to_unlock_mode);

	mem_timings.slow_dll_ctrl &= 0xff00;	/* Keep lock value */



	/* Turn status into unlock ctrl */

	mem_timings.slow_dll_ctrl |=

		((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));



	/* 90 degree phase for anything below 133Mhz */

	mem_timings.slow_dll_ctrl |= (1 << 1);

}



static u32 omap2_reprogram_sdrc(u32 level, u32 force)

{

	u32 slow_dll_ctrl, fast_dll_ctrl, m_type;

	u32 prev = curr_perf_level, flags;



	if ((curr_perf_level == level) && !force)

		return prev;



	m_type = omap2_memory_get_type();

	slow_dll_ctrl = omap2_memory_get_slow_dll_ctrl();

	fast_dll_ctrl = omap2_memory_get_fast_dll_ctrl();



	if (level == PRCM_HALF_SPEED) {

		local_irq_save(flags);

		PRCM_VOLTSETUP = 0xffff;

		omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED,

					  mem_timings.slow_dll_ctrl,

					  mem_timings.m_type);

					  slow_dll_ctrl, m_type);

		curr_perf_level = PRCM_HALF_SPEED;

		local_irq_restore(flags);

	}
@@ -461,8 +411,7 @@ static u32 omap2_reprogram_sdrc(u32 level, u32 force) 
		local_irq_save(flags);

		PRCM_VOLTSETUP = 0xffff;

		omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED,

					  mem_timings.fast_dll_ctrl,

					  mem_timings.m_type);

					  fast_dll_ctrl, m_type);

		curr_perf_level = PRCM_FULL_SPEED;

		local_irq_restore(flags);

	}
@@ -650,7 +599,7 @@ static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask, 
		case 13:				/* dss2 */

			mask = 0x1; break;

		case 25:				/* usb */

			mask = 0xf; break;

			mask = 0x7; break;

		}

	}

arch/arm/mach-omap2/clock.h

+19 −18
Original line number Diff line number Diff line
@@ -33,20 +33,6 @@ static u32 omap2_clksel_get_divisor(struct clk *clk); 
#define RATE_IN_242X	(1 << 0)

#define RATE_IN_243X	(1 << 1)



/* Memory timings */

#define M_DDR		1

#define M_LOCK_CTRL	(1 << 2)

#define M_UNLOCK	0

#define M_LOCK		1



struct memory_timings {

	u32 m_type;		/* ddr = 1, sdr = 0 */

	u32 dll_mode;		/* use lock mode = 1, unlock mode = 0 */

	u32 slow_dll_ctrl;	/* unlock mode, dll value for slow speed */

	u32 fast_dll_ctrl;	/* unlock mode, dll value for fast speed */

	u32 base_cs;		/* base chip select to use for calculations */

};



/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.

 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP

 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
@@ -731,6 +717,16 @@ static struct clk sys_clkout2 = { 
	.recalc		= &omap2_clksel_recalc,

};



static struct clk emul_ck = {

	.name		= "emul_ck",

	.parent		= &func_54m_ck,

	.flags		= CLOCK_IN_OMAP242X,

	.enable_reg	= (void __iomem *)&PRCM_CLKEMUL_CTRL,

	.enable_bit	= 0,

	.recalc		= &omap2_propagate_rate,



};



/*

 * MPU clock domain

 *	Clocks:
@@ -1702,7 +1698,8 @@ static struct clk hdq_fck = { 
};



static struct clk i2c2_ick = {

	.name		= "i2c2_ick",

	.name		= "i2c_ick",

	.id		= 2,

	.parent		= &l4_ck,

	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,

	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
@@ -1711,7 +1708,8 @@ static struct clk i2c2_ick = { 
};



static struct clk i2c2_fck = {

	.name		= "i2c2_fck",

	.name		= "i2c_fck",

	.id		= 2,

	.parent		= &func_12m_ck,

	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,

	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
@@ -1729,7 +1727,8 @@ static struct clk i2chs2_fck = { 
};



static struct clk i2c1_ick = {

	.name		= "i2c1_ick",

	.name		= "i2c_ick",

	.id		= 1,

	.parent		= &l4_ck,

	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,

	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
@@ -1738,7 +1737,8 @@ static struct clk i2c1_ick = { 
};



static struct clk i2c1_fck = {

	.name		= "i2c1_fck",

	.name		= "i2c_fck",

	.id		= 1,

	.parent		= &func_12m_ck,

	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,

	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
@@ -1971,6 +1971,7 @@ static struct clk *onchip_clks[] = { 
	&wdt1_osc_ck,

	&sys_clkout,

	&sys_clkout2,

	&emul_ck,

	/* mpu domain clocks */

	&mpu_ck,

	/* dsp domain clocks */

arch/arm/mach-omap2/memory.c

0 → 100644
+102 −0
Original line number Diff line number Diff line 
/*

 * linux/arch/arm/mach-omap2/memory.c

 *

 * Memory timing related functions for OMAP24XX

 *

 * Copyright (C) 2005 Texas Instruments Inc.

 * Richard Woodruff <r-woodruff2@ti.com>

 *

 * Copyright (C) 2005 Nokia Corporation

 * Tony Lindgren <tony@atomide.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */



#include <linux/config.h>

#include <linux/module.h>

#include <linux/kernel.h>

#include <linux/device.h>

#include <linux/list.h>

#include <linux/errno.h>

#include <linux/delay.h>

#include <linux/clk.h>



#include <asm/io.h>



#include <asm/arch/clock.h>

#include <asm/arch/sram.h>



#include "prcm-regs.h"

#include "memory.h"



static struct memory_timings mem_timings;



u32 omap2_memory_get_slow_dll_ctrl(void)

{

	return mem_timings.slow_dll_ctrl;

}



u32 omap2_memory_get_fast_dll_ctrl(void)

{

	return mem_timings.fast_dll_ctrl;

}



u32 omap2_memory_get_type(void)

{

	return mem_timings.m_type;

}



void omap2_init_memory_params(u32 force_lock_to_unlock_mode)

{

	unsigned long dll_cnt;

	u32 fast_dll = 0;



	mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */



	/* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.

	 * In the case of 2422, its ok to use CS1 instead of CS0.

	 */

	if (cpu_is_omap2422())

		mem_timings.base_cs = 1;

	else

		mem_timings.base_cs = 0;



	if (mem_timings.m_type != M_DDR)

		return;



	/* With DDR we need to determine the low frequency DLL value */

	if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))

		mem_timings.dll_mode = M_UNLOCK;

	else

		mem_timings.dll_mode = M_LOCK;



	if (mem_timings.base_cs == 0) {

		fast_dll = SDRC_DLLA_CTRL;

		dll_cnt = SDRC_DLLA_STATUS & 0xff00;

	} else {

		fast_dll = SDRC_DLLB_CTRL;

		dll_cnt = SDRC_DLLB_STATUS & 0xff00;

	}

	if (force_lock_to_unlock_mode) {

		fast_dll &= ~0xff00;

		fast_dll |= dll_cnt;		/* Current lock mode */

	}

	/* set fast timings with DLL filter disabled */

	mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));



	/* No disruptions, DDR will be offline & C-ABI not followed */

	omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,

			    mem_timings.fast_dll_ctrl,

			    mem_timings.base_cs,

			    force_lock_to_unlock_mode);

	mem_timings.slow_dll_ctrl &= 0xff00;	/* Keep lock value */



	/* Turn status into unlock ctrl */

	mem_timings.slow_dll_ctrl |=

		((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));



	/* 90 degree phase for anything below 133Mhz + disable DLL filter */

	mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));

}