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Commit b8168d1e authored by Paul Walmsley's avatar Paul Walmsley Committed by Russell King
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[ARM] OMAP3 clock: DPLL{1,2}_FCLK clksel can divide by 4 



OMAP34xx ES2 TRM Delta G to H states that the divider for DPLL1_FCLK and
DPLL2_FCLK can divide by 4 in addition to dividing by 1 and 2. Encode this
into the OMAP3 clock framework.

linux-omap source commit is 050684c18f2ea0b08fdd5233a0cd3c7f96e00a0e.

Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent f0587b63

arch/arm/mach-omap2/clock34xx.h

+16 −4
Original line number Original line Diff line number Diff line
@@ -1060,8 +1060,15 @@ static struct clk corex2_fck = { 




/* DPLL power domain clock controls */

/* DPLL power domain clock controls */





static const struct clksel div2_core_clksel[] = {

static const struct clksel_rate div4_rates[] = {

	{ .parent = &core_ck, .rates = div2_rates },

	{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },

	{ .div = 2, .val = 2, .flags = RATE_IN_343X },

	{ .div = 4, .val = 4, .flags = RATE_IN_343X },

	{ .div = 0 }

};



static const struct clksel div4_core_clksel[] = {

	{ .parent = &core_ck, .rates = div4_rates },

	{ .parent = NULL }

	{ .parent = NULL }

};

};
@@ -1076,7 +1083,7 @@ static struct clk dpll1_fck = { 
	.init		= &omap2_init_clksel_parent,

	.init		= &omap2_init_clksel_parent,

	.clksel_reg	= OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),

	.clksel_reg	= OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),

	.clksel_mask	= OMAP3430_MPU_CLK_SRC_MASK,

	.clksel_mask	= OMAP3430_MPU_CLK_SRC_MASK,

	.clksel		= div2_core_clksel,

	.clksel		= div4_core_clksel,

	.flags		= RATE_PROPAGATES,

	.flags		= RATE_PROPAGATES,

	.recalc		= &omap2_clksel_recalc,

	.recalc		= &omap2_clksel_recalc,

};

};
@@ -1151,7 +1158,7 @@ static struct clk dpll2_fck = { 
	.init		= &omap2_init_clksel_parent,

	.init		= &omap2_init_clksel_parent,

	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),

	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),

	.clksel_mask	= OMAP3430_IVA2_CLK_SRC_MASK,

	.clksel_mask	= OMAP3430_IVA2_CLK_SRC_MASK,

	.clksel		= div2_core_clksel,

	.clksel		= div4_core_clksel,

	.flags		= RATE_PROPAGATES,

	.flags		= RATE_PROPAGATES,

	.recalc		= &omap2_clksel_recalc,

	.recalc		= &omap2_clksel_recalc,

};

};
@@ -1187,6 +1194,11 @@ static struct clk iva2_ck = { 




/* Common interface clocks */

/* Common interface clocks */





static const struct clksel div2_core_clksel[] = {

	{ .parent = &core_ck, .rates = div2_rates },

	{ .parent = NULL }

};



static struct clk l3_ick = {

static struct clk l3_ick = {

	.name		= "l3_ick",

	.name		= "l3_ick",

	.ops		= &clkops_null,

	.ops		= &clkops_null,