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Commit b7883a1c authored by Andi Kleen's avatar Andi Kleen Committed by Ingo Molnar
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perf/x86: Handle multiple umask bits for BDW CYCLE_ACTIVITY.* 



The earlier constraint fix for Broadwell CYCLE_ACTIVITY.*
forced umask 8 to counter 2. For this it used UEVENT,
to match the complete umask.

The event list for Broadwell has an additional
STALLS_L1D_PENDIND event that uses umask 8, but also
sets other bits in the umask.  The earlier strict umask match
didn't handle this case.

Add a new UBIT_EVENT constraint macro that only matches
the specified bits in the umask. Then use that macro
to handle CYCLE_ACTIVITY.* on Broadwell.

The documented event also uses cmask, but there's no
need to let the event scheduler know about the cmask,
as the scheduling restriction is only tied to the umask.

Reported-by: default avatarGrant Ayers <ayers@cs.stanford.edu>
Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: http://lkml.kernel.org/r/1447719667-9998-1-git-send-email-andi@firstfloor.org


[ Filled in the missing email address of Grant Ayers - hopefully I got the right one. ]
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent da06a43d

arch/x86/kernel/cpu/perf_event.h

+4 −0
Original line number Diff line number Diff line
@@ -318,6 +318,10 @@ struct cpu_hw_events { 
#define INTEL_UEVENT_CONSTRAINT(c, n)	\

	EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)



/* Constraint on specific umask bit only + event */

#define INTEL_UBIT_EVENT_CONSTRAINT(c, n)	\

	EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c))



/* Like UEVENT_CONSTRAINT, but match flags too */

#define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n)	\

	EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)

arch/x86/kernel/cpu/perf_event_intel.c

+1 −1
Original line number Diff line number Diff line
@@ -255,7 +255,7 @@ struct event_constraint intel_bdw_event_constraints[] = { 
	FIXED_EVENT_CONSTRAINT(0x003c, 1),	/* CPU_CLK_UNHALTED.CORE */

	FIXED_EVENT_CONSTRAINT(0x0300, 2),	/* CPU_CLK_UNHALTED.REF */

	INTEL_UEVENT_CONSTRAINT(0x148, 0x4),	/* L1D_PEND_MISS.PENDING */

	INTEL_UEVENT_CONSTRAINT(0x8a3, 0x4),	/* CYCLE_ACTIVITY.CYCLES_L1D_MISS */

	INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4),	/* CYCLE_ACTIVITY.CYCLES_L1D_MISS */

	EVENT_CONSTRAINT_END

};