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Commit b76f1529 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/disp: allow user direct access to channel control registers 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 648d4dfd

drivers/gpu/drm/nouveau/core/engine/disp/nv50.c

+15 −0
Original line number Diff line number Diff line
@@ -82,6 +82,16 @@ nv50_disp_chan_destroy(struct nv50_disp_chan *chan) 
	nouveau_namedb_destroy(&chan->base);

}



int

nv50_disp_chan_map(struct nouveau_object *object, u64 *addr, u32 *size)

{

	struct nv50_disp_chan *chan = (void *)object;

	*addr = nv_device_resource_start(nv_device(object), 0) +

		0x640000 + (chan->chid * 0x1000);

	*size = 0x001000;

	return 0;

}



u32

nv50_disp_chan_rd32(struct nouveau_object *object, u64 addr)

{
@@ -496,6 +506,7 @@ nv50_disp_mast_ofuncs = { 
	.base.dtor = nv50_disp_dmac_dtor,

	.base.init = nv50_disp_mast_init,

	.base.fini = nv50_disp_mast_fini,

	.base.map  = nv50_disp_chan_map,

	.base.rd32 = nv50_disp_chan_rd32,

	.base.wr32 = nv50_disp_chan_wr32,

	.chid = 0,
@@ -596,6 +607,7 @@ nv50_disp_sync_ofuncs = { 
	.base.dtor = nv50_disp_dmac_dtor,

	.base.init = nv50_disp_dmac_init,

	.base.fini = nv50_disp_dmac_fini,

	.base.map  = nv50_disp_chan_map,

	.base.rd32 = nv50_disp_chan_rd32,

	.base.wr32 = nv50_disp_chan_wr32,

	.chid = 1,
@@ -684,6 +696,7 @@ nv50_disp_ovly_ofuncs = { 
	.base.dtor = nv50_disp_dmac_dtor,

	.base.init = nv50_disp_dmac_init,

	.base.fini = nv50_disp_dmac_fini,

	.base.map  = nv50_disp_chan_map,

	.base.rd32 = nv50_disp_chan_rd32,

	.base.wr32 = nv50_disp_chan_wr32,

	.chid = 3,
@@ -800,6 +813,7 @@ nv50_disp_oimm_ofuncs = { 
	.base.dtor = nv50_disp_pioc_dtor,

	.base.init = nv50_disp_pioc_init,

	.base.fini = nv50_disp_pioc_fini,

	.base.map  = nv50_disp_chan_map,

	.base.rd32 = nv50_disp_chan_rd32,

	.base.wr32 = nv50_disp_chan_wr32,

	.chid = 5,
@@ -846,6 +860,7 @@ nv50_disp_curs_ofuncs = { 
	.base.dtor = nv50_disp_pioc_dtor,

	.base.init = nv50_disp_pioc_init,

	.base.fini = nv50_disp_pioc_fini,

	.base.map  = nv50_disp_chan_map,

	.base.rd32 = nv50_disp_chan_rd32,

	.base.wr32 = nv50_disp_chan_wr32,

	.chid = 7,

drivers/gpu/drm/nouveau/core/engine/disp/nv50.h

+1 −0
Original line number Diff line number Diff line
@@ -116,6 +116,7 @@ struct nv50_disp_chan { 
	int chid;

};



int  nv50_disp_chan_map(struct nouveau_object *, u64 *, u32 *);

u32  nv50_disp_chan_rd32(struct nouveau_object *, u64);

void nv50_disp_chan_wr32(struct nouveau_object *, u64, u32);

drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c

+5 −0
Original line number Diff line number Diff line
@@ -326,6 +326,7 @@ nvd0_disp_mast_ofuncs = { 
	.base.dtor = nv50_disp_dmac_dtor,

	.base.init = nvd0_disp_mast_init,

	.base.fini = nvd0_disp_mast_fini,

	.base.map  = nv50_disp_chan_map,

	.base.rd32 = nv50_disp_chan_rd32,

	.base.wr32 = nv50_disp_chan_wr32,

	.chid = 0,
@@ -418,6 +419,7 @@ nvd0_disp_sync_ofuncs = { 
	.base.dtor = nv50_disp_dmac_dtor,

	.base.init = nvd0_disp_dmac_init,

	.base.fini = nvd0_disp_dmac_fini,

	.base.map  = nv50_disp_chan_map,

	.base.rd32 = nv50_disp_chan_rd32,

	.base.wr32 = nv50_disp_chan_wr32,

	.chid = 1,
@@ -497,6 +499,7 @@ nvd0_disp_ovly_ofuncs = { 
	.base.dtor = nv50_disp_dmac_dtor,

	.base.init = nvd0_disp_dmac_init,

	.base.fini = nvd0_disp_dmac_fini,

	.base.map  = nv50_disp_chan_map,

	.base.rd32 = nv50_disp_chan_rd32,

	.base.wr32 = nv50_disp_chan_wr32,

	.chid = 5,
@@ -567,6 +570,7 @@ nvd0_disp_oimm_ofuncs = { 
	.base.dtor = nv50_disp_pioc_dtor,

	.base.init = nvd0_disp_pioc_init,

	.base.fini = nvd0_disp_pioc_fini,

	.base.map  = nv50_disp_chan_map,

	.base.rd32 = nv50_disp_chan_rd32,

	.base.wr32 = nv50_disp_chan_wr32,

	.chid = 9,
@@ -582,6 +586,7 @@ nvd0_disp_curs_ofuncs = { 
	.base.dtor = nv50_disp_pioc_dtor,

	.base.init = nvd0_disp_pioc_init,

	.base.fini = nvd0_disp_pioc_fini,

	.base.map  = nv50_disp_chan_map,

	.base.rd32 = nv50_disp_chan_rd32,

	.base.wr32 = nv50_disp_chan_wr32,

	.chid = 13,

drivers/gpu/drm/nouveau/nv50_display.c

+3 −1
Original line number Diff line number Diff line
@@ -69,9 +69,11 @@ nv50_chan_create(struct nvif_object *disp, const u32 *oclass, u8 head, 
		int ret = nvif_object_init(disp, NULL, (oclass[0] << 16) | head,

					   oclass[0], data, size,

					  &chan->user);

		if (oclass++, ret == 0)

		if (oclass++, ret == 0) {

			nvif_object_map(&chan->user);

			return ret;

		}

	}

	return -ENOSYS;

}