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Commit b6e89b21 authored by Dinh Nguyen's avatar Dinh Nguyen Committed by Sascha Hauer
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ARM: mx51: Add entry for gpc_dvfs_clk 



For MX51 SRPG, we need to turn on the GPC clock in order to set the
SRPG registers.

Signed-off-by: default avatarDinh Nguyen <Dinh.Nguyen@freescale.com>
Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
parent 16f246e6

arch/arm/mach-mx5/clock-mx51-mx53.c

+8 −0
Original line number Diff line number Diff line
@@ -865,6 +865,13 @@ static struct clk aips_tz2_clk = { 
	.disable = _clk_ccgr_disable_inwait,

};



static struct clk gpc_dvfs_clk = {

	.enable_reg = MXC_CCM_CCGR5,

	.enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,

	.enable = _clk_ccgr_enable,

	.disable = _clk_ccgr_disable,

};



static struct clk gpt_32k_clk = {

	.id = 0,

	.parent = &ckil_clk,
@@ -1448,6 +1455,7 @@ static struct clk_lookup mx51_lookups[] = { 
	_REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk)

	_REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk)

	_REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk)

	_REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk)

};



static struct clk_lookup mx53_lookups[] = {