Commit b6e742f6 authored May 09, 2015 by Damien Lespiau Committed by Daniel Vetter May 20, 2015

drm/i915: Be optimistic about future display engines having 7 WM levels



As we're doing throughout the code, being optimistic that platform n + 1
will mostly reuse the same things as platform n allows us to minimize
the enabling work needed.

This time, it's about the number of WM levels.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

parent 49d6fa21

drivers/gpu/drm/i915/intel_pm.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -1946,7 +1946,7 @@ static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
		int ilk_wm_max_level(const struct drm_device *dev)
		{
		/* how many WM levels are we expecting */
		if (IS_GEN9(dev))
		if (INTEL_INFO(dev)->gen >= 9)
		return 7;
		else if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev))
		return 4;