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Commit b699ddd1 authored by Santosh Shilimkar's avatar Santosh Shilimkar
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ARM: OMAP4+: Move the CPU wakeup prepare code under smp_prepare_cpus() 



Move the secondary CPU wakeup prepare code under smp_prepare_cpus() where it
belongs. It was remainder of the pen release code which was borrowed from
ARM code initially.

While at it drop the un-necessary sev() and barrier which was under
prepare code.

Signed-off-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
parent 2f82bd78

arch/arm/mach-omap2/omap-smp.c

+20 −31
Original line number Diff line number Diff line
@@ -164,36 +164,6 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct * 
	return 0;

}



static void __init wakeup_secondary(void)

{

	void *startup_addr = omap_secondary_startup;

	void __iomem *base = omap_get_wakeupgen_base();



	if (cpu_is_omap446x()) {

		startup_addr = omap_secondary_startup_4460;

		pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;

	}



	/*

	 * Write the address of secondary startup routine into the

	 * AuxCoreBoot1 where ROM code will jump and start executing

	 * on secondary core once out of WFE

	 * A barrier is added to ensure that write buffer is drained

	 */

	if (omap_secure_apis_support())

		omap_auxcoreboot_addr(virt_to_phys(startup_addr));

	else

		__raw_writel(virt_to_phys(omap5_secondary_startup),

						base + OMAP_AUX_CORE_BOOT_1);



	/*

	 * Send a 'sev' to wake the secondary core from WFE.

	 * Drain the outstanding writes to memory

	 */

	dsb_sev();

	mb();

}



/*

 * Initialise the CPU possible map early - this describes the CPUs

 * which may be present or become present in the system.
@@ -229,6 +199,8 @@ static void __init omap4_smp_init_cpus(void) 


static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)

{

	void *startup_addr = omap_secondary_startup;

	void __iomem *base = omap_get_wakeupgen_base();



	/*

	 * Initialise the SCU and wake up the secondary core using
@@ -236,7 +208,24 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) 
	 */

	if (scu_base)

		scu_enable(scu_base);

	wakeup_secondary();



	if (cpu_is_omap446x()) {

		startup_addr = omap_secondary_startup_4460;

		pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;

	}



	/*

	 * Write the address of secondary startup routine into the

	 * AuxCoreBoot1 where ROM code will jump and start executing

	 * on secondary core once out of WFE

	 * A barrier is added to ensure that write buffer is drained

	 */

	if (omap_secure_apis_support())

		omap_auxcoreboot_addr(virt_to_phys(startup_addr));

	else

		__raw_writel(virt_to_phys(omap5_secondary_startup),

						base + OMAP_AUX_CORE_BOOT_1);



}



struct smp_operations omap4_smp_ops __initdata = {