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Commit b6884a17 authored by Patrick Boettcher's avatar Patrick Boettcher Committed by Mauro Carvalho Chehab
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V4L/DVB (5954): Sync with DiBcom Driver Release 2.1.3 + some improvements 



This changesets syncs the OpenSource driver for DiBcom demodulators
with version 2.1.3 of DiBcom reference driver. There were some
improvements since the last release for linux-dvb, e.g.:

- stepped AGC startup
- less space for initialization
- diversity synchronization

Furthermore this changeset contains the following things:

- latest AGC settings for MT2266-based devices (namely Nova-TD and other) will improve the sensitivity
- support for STK7700D reference design in dib0700-devices
- remove some line-breaks when debugging is enabled
- getting rid of layer between frontend_parameters and ofdm_channel used in dib*-drivers

Signed-off-by: default avatarPatrick Boettcher <pboettcher@dibcom.fr>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@infradead.org>
parent b2a65760

drivers/media/dvb/dvb-usb/dib0700_devices.c

+101 −47
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ 
 *	under the terms of the GNU General Public License as published by the Free

 *	Software Foundation, version 2.

 *

 *  Copyright (C) 2005-6 DiBcom, SA

 *  Copyright (C) 2005-7 DiBcom, SA

 */

#include "dib0700.h"
@@ -99,9 +99,54 @@ static int bristol_tuner_attach(struct dvb_usb_adapter *adap) 


/* STK7700D: Pinnacle Dual DVB-T Diversity */



static struct dibx000_agc_config stk7700d_7000p_mt2266_agc_config = {

	BAND_UHF/* | BAND_VHF*/,

	0xE64, // setup

/* MT226x */

static struct dibx000_agc_config stk7700d_7000p_mt2266_agc_config[2] = {

	{

		BAND_UHF, // band_caps



		/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=1, P_agc_inv_pwm2=1,

		* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */

		(0 << 15) | (0 << 14) | (1 << 11) | (1 << 10) | (1 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), // setup



		1130,  // inv_gain

		21,  // time_stabiliz



		0,  // alpha_level

		118,  // thlock



		0,     // wbd_inv

		3530,  // wbd_ref

		1,     // wbd_sel

		0,     // wbd_alpha



		65535,  // agc1_max

		33770,  // agc1_min

		65535,  // agc2_max

		23592,  // agc2_min



		0,    // agc1_pt1

		62,   // agc1_pt2

		255,  // agc1_pt3

		64,   // agc1_slope1

		64,   // agc1_slope2

		132,  // agc2_pt1

		192,  // agc2_pt2

		80,   // agc2_slope1

		80,   // agc2_slope2



		17,  // alpha_mant

		27,  // alpha_exp

		23,  // beta_mant

		51,  // beta_exp



		1,  // perform_agc_softsplit

	}, {

		BAND_VHF | BAND_LBAND, // band_caps



		/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=1, P_agc_inv_pwm2=1,

		* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=2, P_agc_write=0 */

		(0 << 15) | (0 << 14) | (1 << 11) | (1 << 10) | (1 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), // setup



		2372, // inv_gain

		21,   // time_stabiliz
@@ -109,14 +154,15 @@ static struct dibx000_agc_config stk7700d_7000p_mt2266_agc_config = { 
		118,  // thlock



		0,    // wbd_inv

	0,    // wbd_ref

	0,    // wbd_sel

		3530, // wbd_ref

		1,     // wbd_sel

		0,    // wbd_alpha



		65535, // agc1_max

		0,     // agc1_min

		65535, // agc2_max

		23592, // agc2_min



		0,    // agc1_pt1

		128,  // agc1_pt2

		128,  // agc1_pt3
@@ -129,11 +175,11 @@ static struct dibx000_agc_config stk7700d_7000p_mt2266_agc_config = { 


		17,  // alpha_mant

		27,  // alpha_exp



		23,  // beta_mant

		51,  // beta_exp



	0, // perform_agc_softsplit : 1 en vrai!

		1,  // perform_agc_softsplit

	}

};



static struct dibx000_bandwidth_config stk7700d_mt2266_pll_config = {
@@ -150,23 +196,25 @@ static struct dib7000p_config stk7700d_dib7000p_mt2266_config[] = { 
		.hostbus_diversity = 1,

		.tuner_is_baseband = 1,



		.agc = &stk7700d_7000p_mt2266_agc_config,

		.agc_config_count = 2,

		.agc = stk7700d_7000p_mt2266_agc_config,

		.bw  = &stk7700d_mt2266_pll_config,



		.gpio_dir = DIB7000M_GPIO_DEFAULT_DIRECTIONS,

		.gpio_val = DIB7000M_GPIO_DEFAULT_VALUES,

		.gpio_pwm_pos = DIB7000M_GPIO_DEFAULT_PWM_POS,

		.gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,

		.gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,

		.gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,

	},

	{	.output_mpeg2_in_188_bytes = 1,

		.hostbus_diversity = 1,

		.tuner_is_baseband = 1,



		.agc = &stk7700d_7000p_mt2266_agc_config,

		.agc_config_count = 2,

		.agc = stk7700d_7000p_mt2266_agc_config,

		.bw  = &stk7700d_mt2266_pll_config,



		.gpio_dir = DIB7000M_GPIO_DEFAULT_DIRECTIONS,

		.gpio_val = DIB7000M_GPIO_DEFAULT_VALUES,

		.gpio_pwm_pos = DIB7000M_GPIO_DEFAULT_PWM_POS,

		.gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,

		.gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,

		.gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,

	}

};
@@ -211,7 +259,7 @@ static int stk7700d_tuner_attach(struct dvb_usb_adapter *adap) 


static u8 rc_request[] = { REQUEST_POLL_RC, 0 };



int stk7700d_rc_query(struct dvb_usb_device *d, u32 *event, int *state)

static int stk7700d_rc_query(struct dvb_usb_device *d, u32 *event, int *state)

{

	u8 key[4];

	int i;
@@ -241,7 +289,7 @@ int stk7700d_rc_query(struct dvb_usb_device *d, u32 *event, int *state) 


#define KEY_MAP_SIZE (25+48)



struct dvb_usb_rc_key stk7700d_rc_keys[] = {

static struct dvb_usb_rc_key stk7700d_rc_keys[] = {

	/* Key codes for the tiny Pinnacle remote*/

	{ 0x07, 0x00, KEY_MUTE },

	{ 0x07, 0x01, KEY_MENU }, // Pinnacle logo
@@ -436,6 +484,7 @@ static struct dib7000m_config stk7700p_dib7000m_config = { 
static struct dib7000p_config stk7700p_dib7000p_config = {

	.output_mpeg2_in_188_bytes = 1,



	.agc_config_count = 1,

	.agc = &stk7700p_7000p_mt2060_agc_config,

	.bw  = &stk7700p_pll_config,
@@ -506,6 +555,7 @@ struct usb_device_id dib0700_usb_id_table[] = { 
		{ USB_DEVICE(USB_VID_PINNACLE,  USB_PID_PINNACLE_PCTV2000E) },

		{ USB_DEVICE(USB_VID_TERRATEC,  USB_PID_TERRATEC_CINERGY_DT_XS_DIVERSITY) },

		{ USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_NOVA_TD_STICK) },

		{ USB_DEVICE(USB_VID_DIBCOM,    USB_PID_DIBCOM_STK7700D) },

		{ }		/* Terminating entry */

};

MODULE_DEVICE_TABLE(usb, dib0700_usb_id_table);
@@ -615,7 +665,7 @@ struct dvb_usb_device_properties dib0700_devices[] = { 
			}

		},



		.num_device_descs = 3,

		.num_device_descs = 4,

		.devices = {

			{   "Pinnacle PCTV 2000e",

				{ &dib0700_usb_id_table[11], NULL },
@@ -629,6 +679,10 @@ struct dvb_usb_device_properties dib0700_devices[] = { 
				{ &dib0700_usb_id_table[13], NULL },

				{ NULL },

			},

			{   "DiBcom STK7700D",

				{ &dib0700_usb_id_table[14], NULL },

				{ NULL },

			},

		},

		.rc_interval      = DEFAULT_RC_INTERVAL,

		.rc_key_map       = stk7700d_rc_keys,

drivers/media/dvb/dvb-usb/dvb-usb-ids.h

+1 −0
Original line number Diff line number Diff line
@@ -67,6 +67,7 @@ 
#define USB_PID_DIBCOM_MOD3001_WARM			0x0bc7

#define USB_PID_DIBCOM_STK7700P				0x1e14

#define USB_PID_DIBCOM_STK7700P_PC			0x1e78

#define USB_PID_DIBCOM_STK7700D				0x1ef0

#define USB_PID_DIBCOM_ANCHOR_2135_COLD			0x2131

#define USB_PID_DPOSH_M9206_COLD			0x9206

#define USB_PID_DPOSH_M9206_WARM			0xa090

drivers/media/dvb/frontends/dib3000mc.c

+104 −66
Original line number Diff line number Diff line 
/*

 * Driver for DiBcom DiB3000MC/P-demodulator.

 *

 * Copyright (C) 2004-6 DiBcom (http://www.dibcom.fr/)

 * Copyright (C) 2004-7 DiBcom (http://www.dibcom.fr/)

 * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@desy.de)

 *

 * This code is partially based on the previous dib3000mc.c .
@@ -26,7 +26,7 @@ static int debug; 
module_param(debug, int, 0644);

MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");



#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB3000MC/P:"); printk(args); } } while (0)

#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB3000MC/P:"); printk(args); printk("\n"); } } while (0)



struct dib3000mc_state {

	struct dvb_frontend demod;
@@ -71,7 +71,6 @@ static int dib3000mc_write_word(struct dib3000mc_state *state, u16 reg, u16 val) 
	return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;

}





static int dib3000mc_identify(struct dib3000mc_state *state)

{

	u16 value;
@@ -92,7 +91,7 @@ static int dib3000mc_identify(struct dib3000mc_state *state) 
	return 0;

}



static int dib3000mc_set_timing(struct dib3000mc_state *state, s16 nfft, u8 bw, u8 update_offset)

static int dib3000mc_set_timing(struct dib3000mc_state *state, s16 nfft, u32 bw, u8 update_offset)

{

	u32 timf;
@@ -103,7 +102,7 @@ static int dib3000mc_set_timing(struct dib3000mc_state *state, s16 nfft, u8 bw, 
	} else

		timf = state->timf;



	timf *= (BW_INDEX_TO_KHZ(bw) / 1000);

	timf *= (bw / 1000);



	if (update_offset) {

		s16 tim_offs = dib3000mc_read_word(state, 416);
@@ -111,17 +110,17 @@ static int dib3000mc_set_timing(struct dib3000mc_state *state, s16 nfft, u8 bw, 
		if (tim_offs &  0x2000)

			tim_offs -= 0x4000;



		if (nfft == 0)

		if (nfft == TRANSMISSION_MODE_2K)

			tim_offs *= 4;



		timf += tim_offs;

		state->timf = timf / (BW_INDEX_TO_KHZ(bw) / 1000);

		state->timf = timf / (bw / 1000);

	}



	dprintk("timf: %d\n", timf);



	dib3000mc_write_word(state, 23, timf >> 16);

	dib3000mc_write_word(state, 24, timf & 0xffff);

	dib3000mc_write_word(state, 23, (u16) (timf >> 16));

	dib3000mc_write_word(state, 24, (u16) (timf      ) & 0xffff);



	return 0;

}
@@ -209,31 +208,30 @@ static int dib3000mc_set_output_mode(struct dib3000mc_state *state, int mode) 
	return ret;

}



static int dib3000mc_set_bandwidth(struct dvb_frontend *demod, u8 bw)

static int dib3000mc_set_bandwidth(struct dib3000mc_state *state, u32 bw)

{

	struct dib3000mc_state *state = demod->demodulator_priv;

	u16 bw_cfg[6] = { 0 };

	u16 imp_bw_cfg[3] = { 0 };

	u16 reg;



/* settings here are for 27.7MHz */

	switch (bw) {

		case BANDWIDTH_8_MHZ:

		case 8000:

			bw_cfg[0] = 0x0019; bw_cfg[1] = 0x5c30; bw_cfg[2] = 0x0054; bw_cfg[3] = 0x88a0; bw_cfg[4] = 0x01a6; bw_cfg[5] = 0xab20;

			imp_bw_cfg[0] = 0x04db; imp_bw_cfg[1] = 0x00db; imp_bw_cfg[2] = 0x00b7;

			break;



		case BANDWIDTH_7_MHZ:

		case 7000:

			bw_cfg[0] = 0x001c; bw_cfg[1] = 0xfba5; bw_cfg[2] = 0x0060; bw_cfg[3] = 0x9c25; bw_cfg[4] = 0x01e3; bw_cfg[5] = 0x0cb7;

			imp_bw_cfg[0] = 0x04c0; imp_bw_cfg[1] = 0x00c0; imp_bw_cfg[2] = 0x00a0;

			break;



		case BANDWIDTH_6_MHZ:

		case 6000:

			bw_cfg[0] = 0x0021; bw_cfg[1] = 0xd040; bw_cfg[2] = 0x0070; bw_cfg[3] = 0xb62b; bw_cfg[4] = 0x0233; bw_cfg[5] = 0x8ed5;

			imp_bw_cfg[0] = 0x04a5; imp_bw_cfg[1] = 0x00a5; imp_bw_cfg[2] = 0x0089;

			break;



		case 255 /* BANDWIDTH_5_MHZ */:

		case 5000:

			bw_cfg[0] = 0x0028; bw_cfg[1] = 0x9380; bw_cfg[2] = 0x0087; bw_cfg[3] = 0x4100; bw_cfg[4] = 0x02a4; bw_cfg[5] = 0x4500;

			imp_bw_cfg[0] = 0x0489; imp_bw_cfg[1] = 0x0089; imp_bw_cfg[2] = 0x0072;

			break;
@@ -257,7 +255,7 @@ static int dib3000mc_set_bandwidth(struct dvb_frontend *demod, u8 bw) 
		dib3000mc_write_word(state, reg, imp_bw_cfg[reg - 55]);



	// Timing configuration

	dib3000mc_set_timing(state, 0, bw, 0);

	dib3000mc_set_timing(state, TRANSMISSION_MODE_2K, bw, 0);



	return 0;

}
@@ -276,7 +274,7 @@ static void dib3000mc_set_impulse_noise(struct dib3000mc_state *state, u8 mode, 
	for (i = 58; i < 87; i++)

		dib3000mc_write_word(state, i, impulse_noise_val[i-58]);



	if (nfft == 1) {

	if (nfft == TRANSMISSION_MODE_8K) {

		dib3000mc_write_word(state, 58, 0x3b);

		dib3000mc_write_word(state, 84, 0x00);

		dib3000mc_write_word(state, 85, 0x8200);
@@ -376,7 +374,7 @@ static int dib3000mc_init(struct dvb_frontend *demod) 
	// P_search_maxtrial=1

	dib3000mc_write_word(state, 5, 1);



	dib3000mc_set_bandwidth(&state->demod, BANDWIDTH_8_MHZ);

	dib3000mc_set_bandwidth(state, 8000);



	// div_lock_mask

	dib3000mc_write_word(state,  4, 0x814);
@@ -397,7 +395,7 @@ static int dib3000mc_init(struct dvb_frontend *demod) 
	dib3000mc_write_word(state, 180, 0x2FF0);



	// Impulse noise configuration

	dib3000mc_set_impulse_noise(state, 0, 1);

	dib3000mc_set_impulse_noise(state, 0, TRANSMISSION_MODE_8K);



	// output mode set-up

	dib3000mc_set_output_mode(state, OUTMODE_HIGH_Z);
@@ -423,13 +421,13 @@ static void dib3000mc_set_adp_cfg(struct dib3000mc_state *state, s16 qam) 
{

	u16 cfg[4] = { 0 },reg;

	switch (qam) {

		case 0:

		case QPSK:

			cfg[0] = 0x099a; cfg[1] = 0x7fae; cfg[2] = 0x0333; cfg[3] = 0x7ff0;

			break;

		case 1:

		case QAM_16:

			cfg[0] = 0x023d; cfg[1] = 0x7fdf; cfg[2] = 0x00a4; cfg[3] = 0x7ff0;

			break;

		case 2:

		case QAM_64:

			cfg[0] = 0x0148; cfg[1] = 0x7ff0; cfg[2] = 0x00a4; cfg[3] = 0x7ff8;

			break;

	}
@@ -437,11 +435,11 @@ static void dib3000mc_set_adp_cfg(struct dib3000mc_state *state, s16 qam) 
		dib3000mc_write_word(state, reg, cfg[reg - 129]);

}



static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state, struct dibx000_ofdm_channel *chan, u16 seq)

static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state, struct dvb_frontend_parameters *ch, u16 seq)

{

	u16 tmp;



	dib3000mc_set_timing(state, chan->nfft, chan->Bw, 0);

	u16 value;

    dib3000mc_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));

	dib3000mc_set_timing(state, ch->u.ofdm.transmission_mode, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth), 0);



//	if (boost)

//		dib3000mc_write_word(state, 100, (11 << 6) + 6);
@@ -455,7 +453,7 @@ static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state, struct dibx 
	dib3000mc_write_word(state, 26,  0x6680);

	dib3000mc_write_word(state, 29,  0x1273);

	dib3000mc_write_word(state, 33,       5);

	dib3000mc_set_adp_cfg(state, 1);

	dib3000mc_set_adp_cfg(state, QAM_16);

	dib3000mc_write_word(state, 133,  15564);



	dib3000mc_write_word(state, 12 , 0x0);
@@ -470,52 +468,98 @@ static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state, struct dibx 
	dib3000mc_write_word(state, 97,0);

	dib3000mc_write_word(state, 98,0);



	dib3000mc_set_impulse_noise(state, 0, chan->nfft);



	tmp = ((chan->nfft & 0x1) << 7) | (chan->guard << 5) | (chan->nqam << 3) | chan->vit_alpha;

	dib3000mc_write_word(state, 0, tmp);

	dib3000mc_set_impulse_noise(state, 0, ch->u.ofdm.transmission_mode);



	value = 0;

	switch (ch->u.ofdm.transmission_mode) {

		case TRANSMISSION_MODE_2K: value |= (0 << 7); break;

		default:

		case TRANSMISSION_MODE_8K: value |= (1 << 7); break;

	}

	switch (ch->u.ofdm.guard_interval) {

		case GUARD_INTERVAL_1_32: value |= (0 << 5); break;

		case GUARD_INTERVAL_1_16: value |= (1 << 5); break;

		case GUARD_INTERVAL_1_4:  value |= (3 << 5); break;

		default:

		case GUARD_INTERVAL_1_8:  value |= (2 << 5); break;

	}

	switch (ch->u.ofdm.constellation) {

		case QPSK:  value |= (0 << 3); break;

		case QAM_16: value |= (1 << 3); break;

		default:

		case QAM_64: value |= (2 << 3); break;

	}

	switch (HIERARCHY_1) {

		case HIERARCHY_2: value |= 2; break;

		case HIERARCHY_4: value |= 4; break;

		default:

		case HIERARCHY_1: value |= 1; break;

	}

	dib3000mc_write_word(state, 0, value);

	dib3000mc_write_word(state, 5, (1 << 8) | ((seq & 0xf) << 4));



	tmp = (chan->vit_hrch << 4) | (chan->vit_select_hp);

	if (!chan->vit_hrch || (chan->vit_hrch && chan->vit_select_hp))

		tmp |= chan->vit_code_rate_hp << 1;

	else

		tmp |= chan->vit_code_rate_lp << 1;

	dib3000mc_write_word(state, 181, tmp);

	value = 0;

	if (ch->u.ofdm.hierarchy_information == 1)

		value |= (1 << 4);

	if (1 == 1)

		value |= 1;

	switch ((ch->u.ofdm.hierarchy_information == 0 || 1 == 1) ? ch->u.ofdm.code_rate_HP : ch->u.ofdm.code_rate_LP) {

		case FEC_2_3: value |= (2 << 1); break;

		case FEC_3_4: value |= (3 << 1); break;

		case FEC_5_6: value |= (5 << 1); break;

		case FEC_7_8: value |= (7 << 1); break;

		default:

		case FEC_1_2: value |= (1 << 1); break;

	}

	dib3000mc_write_word(state, 181, value);



	// diversity synchro delay

	tmp = dib3000mc_read_word(state, 180) & 0x000f;

	tmp |= ((chan->nfft == 0) ? 64 : 256) * ((1 << (chan->guard)) * 3 / 2) << 4; // add 50% SFN margin

	dib3000mc_write_word(state, 180, tmp);

	// diversity synchro delay add 50% SFN margin

	switch (ch->u.ofdm.transmission_mode) {

		case TRANSMISSION_MODE_8K: value = 256; break;

		case TRANSMISSION_MODE_2K:

		default: value = 64; break;

	}

	switch (ch->u.ofdm.guard_interval) {

		case GUARD_INTERVAL_1_16: value *= 2; break;

		case GUARD_INTERVAL_1_8:  value *= 4; break;

		case GUARD_INTERVAL_1_4:  value *= 8; break;

		default:

		case GUARD_INTERVAL_1_32: value *= 1; break;

	}

	value <<= 4;

	value |= dib3000mc_read_word(state, 180) & 0x000f;

	dib3000mc_write_word(state, 180, value);



	// restart demod

	tmp = dib3000mc_read_word(state, 0);

	dib3000mc_write_word(state, 0, tmp | (1 << 9));

	dib3000mc_write_word(state, 0, tmp);

	value = dib3000mc_read_word(state, 0);

	dib3000mc_write_word(state, 0, value | (1 << 9));

	dib3000mc_write_word(state, 0, value);



	msleep(30);



	dib3000mc_set_impulse_noise(state, state->cfg->impulse_noise_mode, chan->nfft);

	dib3000mc_set_impulse_noise(state, state->cfg->impulse_noise_mode, ch->u.ofdm.transmission_mode);

}



static int dib3000mc_autosearch_start(struct dvb_frontend *demod, struct dibx000_ofdm_channel *chan)

static int dib3000mc_autosearch_start(struct dvb_frontend *demod, struct dvb_frontend_parameters *chan)

{

	struct dib3000mc_state *state = demod->demodulator_priv;

	u16 reg;

//	u32 val;

	struct dibx000_ofdm_channel fchan;

	struct dvb_frontend_parameters schan;



	INIT_OFDM_CHANNEL(&fchan);

	fchan = *chan;

	schan = *chan;



	/* TODO what is that ? */



	/* a channel for autosearch */

	fchan.nfft = 1; fchan.guard = 0; fchan.nqam = 2;

	fchan.vit_alpha = 1; fchan.vit_code_rate_hp = 2; fchan.vit_code_rate_lp = 2;

	fchan.vit_hrch = 0; fchan.vit_select_hp = 1;

	schan.u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;

	schan.u.ofdm.guard_interval = GUARD_INTERVAL_1_32;

	schan.u.ofdm.constellation = QAM_64;

	schan.u.ofdm.code_rate_HP = FEC_2_3;

	schan.u.ofdm.code_rate_LP = FEC_2_3;

	schan.u.ofdm.hierarchy_information = 0;



	dib3000mc_set_channel_cfg(state, &fchan, 11);

	dib3000mc_set_channel_cfg(state, &schan, 11);



	reg = dib3000mc_read_word(state, 0);

	dib3000mc_write_word(state, 0, reg | (1 << 8));
@@ -539,7 +583,7 @@ static int dib3000mc_autosearch_is_irq(struct dvb_frontend *demod) 
	return 0; // still pending

}



static int dib3000mc_tune(struct dvb_frontend *demod, struct dibx000_ofdm_channel *ch)

static int dib3000mc_tune(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch)

{

	struct dib3000mc_state *state = demod->demodulator_priv;
@@ -549,9 +593,8 @@ static int dib3000mc_tune(struct dvb_frontend *demod, struct dibx000_ofdm_channe 
	// activates isi

	dib3000mc_write_word(state, 29, 0x1073);



	dib3000mc_set_adp_cfg(state, (u8)ch->nqam);



	if (ch->nfft == 1) {

	dib3000mc_set_adp_cfg(state, (uint8_t)ch->u.ofdm.constellation);

	if (ch->u.ofdm.transmission_mode == TRANSMISSION_MODE_8K) {

		dib3000mc_write_word(state, 26, 38528);

		dib3000mc_write_word(state, 33, 8);

	} else {
@@ -560,7 +603,7 @@ static int dib3000mc_tune(struct dvb_frontend *demod, struct dibx000_ofdm_channe 
	}



	if (dib3000mc_read_word(state, 509) & 0x80)

		dib3000mc_set_timing(state, ch->nfft, ch->Bw, 1);

		dib3000mc_set_timing(state, ch->u.ofdm.transmission_mode, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth), 1);



	return 0;

}
@@ -632,13 +675,9 @@ static int dib3000mc_set_frontend(struct dvb_frontend* fe, 
				struct dvb_frontend_parameters *fep)

{

	struct dib3000mc_state *state = fe->demodulator_priv;

	struct dibx000_ofdm_channel ch;



	INIT_OFDM_CHANNEL(&ch);

	FEP2DIB(fep,&ch);



	state->current_bandwidth = fep->u.ofdm.bandwidth;

	dib3000mc_set_bandwidth(fe, fep->u.ofdm.bandwidth);

	dib3000mc_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->u.ofdm.bandwidth));



	if (fe->ops.tuner_ops.set_params) {

		fe->ops.tuner_ops.set_params(fe, fep);
@@ -651,7 +690,7 @@ static int dib3000mc_set_frontend(struct dvb_frontend* fe, 
		fep->u.ofdm.code_rate_HP      == FEC_AUTO) {

		int i = 100, found;



		dib3000mc_autosearch_start(fe, &ch);

		dib3000mc_autosearch_start(fe, fep);

		do {

			msleep(1);

			found = dib3000mc_autosearch_is_irq(fe);
@@ -662,13 +701,12 @@ static int dib3000mc_set_frontend(struct dvb_frontend* fe, 
			return 0; // no channel found



		dib3000mc_get_frontend(fe, fep);

		FEP2DIB(fep,&ch);

	}



	/* make this a config parameter */

	dib3000mc_set_output_mode(state, OUTMODE_MPEG2_FIFO);



	return dib3000mc_tune(fe, &ch);

	return dib3000mc_tune(fe, fep);

}



static int dib3000mc_read_status(struct dvb_frontend *fe, fe_status_t *stat)

drivers/media/dvb/frontends/dib7000m.c

+466 −257

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drivers/media/dvb/frontends/dib7000p.c

+587 −273

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