Merge branch 'for-linus' into for-next (b656eba1) · Commits · e / devices / android_kernel_teracube_2e

MAINTAINERS

+1 −1

Original line number	Diff line number	Diff line
		@@ -2743,7 +2743,7 @@ IDE SUBSYSTEM
		P: Bartlomiej Zolnierkiewicz
		M: bzolnier@gmail.com
		L: linux-ide@vger.kernel.org
		T: quilt kernel.org/pub/linux/kernel/people/bart/pata-2.6/
		T: git git://git.kernel.org/pub/scm/linux/kernel/git/bart/ide-2.6.git
		S: Maintained
		F: Documentation/ide/
		F: drivers/ide/

drivers/ide/palm_bk3710.c

+24 −55

Original line number	Diff line number	Diff line
		@@ -42,16 +42,9 @@
		#define BK3710_BMICP 0x00
		#define BK3710_BMISP 0x02
		#define BK3710_BMIDTP 0x04
		#define BK3710_BMICS 0x08
		#define BK3710_BMISS 0x0A
		#define BK3710_BMIDTS 0x0C
		#define BK3710_IDETIMP 0x40
		#define BK3710_IDETIMS 0x42
		#define BK3710_SIDETIM 0x44
		#define BK3710_SLEWCTL 0x45
		#define BK3710_IDESTATUS 0x47
		#define BK3710_UDMACTL 0x48
		#define BK3710_UDMATIM 0x4A
		#define BK3710_MISCCTL 0x50
		#define BK3710_REGSTB 0x54
		#define BK3710_REGRCVR 0x58
		@@ -63,7 +56,6 @@
		#define BK3710_UDMATRP 0x70
		#define BK3710_UDMAENV 0x74
		#define BK3710_IORDYTMP 0x78
		#define BK3710_IORDYTMS 0x7C

		static unsigned ideclk_period; /* in nanoseconds */

		@@ -74,12 +66,12 @@ struct palm_bk3710_udmatiming {
		};

		static const struct palm_bk3710_udmatiming palm_bk3710_udmatimings[6] = {
		{160, 240 / 2,}, /* UDMA Mode 0 */
		{125, 160 / 2,}, /* UDMA Mode 1 */
		{100, 120 / 2,}, /* UDMA Mode 2 */
		{100, 90 / 2,}, /* UDMA Mode 3 */
		{100, 60 / 2,}, /* UDMA Mode 4 */
		{85, 40 / 2,}, /* UDMA Mode 5 */
		{ 160, 240 / 2 }, /* UDMA Mode 0 */
		{ 125, 160 / 2 }, /* UDMA Mode 1 */
		{ 100, 120 / 2 }, /* UDMA Mode 2 */
		{ 100, 90 / 2 }, /* UDMA Mode 3 */
		{ 100, 60 / 2 }, /* UDMA Mode 4 */
		{ 85, 40 / 2 }, /* UDMA Mode 5 */
		};

		static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev,
		@@ -96,11 +88,6 @@ static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev,
		trp = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].rptime,
		ideclk_period) - 1;

		/* udmatim Register */
		val16 = readw(base + BK3710_UDMATIM) & (dev ? 0xFF0F : 0xFFF0);
		val16 \|= (mode << (dev ? 4 : 0));
		writew(val16, base + BK3710_UDMATIM);

		/* udmastb Ultra DMA Access Strobe Width */
		val32 = readl(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8));
		val32 \|= (t0 << (dev ? 8 : 0));
		@@ -161,10 +148,11 @@ static void palm_bk3710_setpiomode(void __iomem base, ide_drive_t mate,
		u32 val32;
		struct ide_timing *t;

		t = ide_timing_find_mode(XFER_PIO_0 + mode);

		/* PIO Data Setup */
		t0 = DIV_ROUND_UP(cycletime, ideclk_period);
		t2 = DIV_ROUND_UP(ide_timing_find_mode(XFER_PIO_0 + mode)->active,
		ideclk_period);
		t2 = DIV_ROUND_UP(t->active, ideclk_period);

		t2i = t0 - t2 - 1;
		t2 -= 1;
		@@ -185,7 +173,6 @@ static void palm_bk3710_setpiomode(void __iomem base, ide_drive_t mate,
		}

		/* TASKFILE Setup */
		t = ide_timing_find_mode(XFER_PIO_0 + mode);
		t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period);
		t2 = DIV_ROUND_UP(t->act8b, ideclk_period);

		@@ -234,42 +221,23 @@ static void palm_bk3710_set_pio_mode(ide_drive_t *drive, u8 pio)
		static void __devinit palm_bk3710_chipinit(void __iomem *base)
		{
		/*
		* enable the reset_en of ATA controller so that when ata signals
		* are brought out, by writing into device config. at that
		* time por_n signal should not be 'Z' and have a stable value.
		* REVISIT: the ATA reset signal needs to be managed through a
		* GPIO, which means it should come from platform_data. Until
		* we get and use such information, we have to trust that things
		* have been reset before we get here.
		*/
		writel(0x0300, base + BK3710_MISCCTL);

		/* wait for some time and deassert the reset of ATA Device. */
		mdelay(100);

		/* Deassert the Reset */
		writel(0x0200, base + BK3710_MISCCTL);

		/*
		* Program the IDETIMP Register Value based on the following assumptions
		*
		* (ATA_IDETIMP_IDEEN , ENABLE ) \|
		* (ATA_IDETIMP_SLVTIMEN , DISABLE) \|
		* (ATA_IDETIMP_RDYSMPL , 70NS) \|
		* (ATA_IDETIMP_RDYRCVRY , 50NS) \|
		* (ATA_IDETIMP_DMAFTIM1 , PIOCOMP) \|
		* (ATA_IDETIMP_PREPOST1 , DISABLE) \|
		* (ATA_IDETIMP_RDYSEN1 , DISABLE) \|
		* (ATA_IDETIMP_PIOFTIM1 , DISABLE) \|
		* (ATA_IDETIMP_DMAFTIM0 , PIOCOMP) \|
		* (ATA_IDETIMP_PREPOST0 , DISABLE) \|
		* (ATA_IDETIMP_RDYSEN0 , DISABLE) \|
		* (ATA_IDETIMP_PIOFTIM0 , DISABLE)
		*/
		writew(0xB388, base + BK3710_IDETIMP);

		/*
		* Configure SIDETIM Register
		* (ATA_SIDETIM_RDYSMPS1 ,120NS ) \|
		* (ATA_SIDETIM_RDYRCYS1 ,120NS )
		*
		* DM6446 silicon rev 2.1 and earlier have no observed net benefit
		* from enabling prefetch/postwrite.
		*/
		writeb(0, base + BK3710_SIDETIM);
		writew(BIT(15), base + BK3710_IDETIMP);

		/*
		* UDMACTL Ultra-ATA DMA Control
		@@ -281,11 +249,11 @@ static void __devinit palm_bk3710_chipinit(void __iomem *base)

		/*
		* MISCCTL Miscellaneous Conrol Register
		* (ATA_MISCCTL_RSTMODEP , 1) \|
		* (ATA_MISCCTL_RESETP , 0) \|
		* (ATA_MISCCTL_HWNHLD1P , 1 cycle)
		* (ATA_MISCCTL_HWNHLD0P , 1 cycle)
		* (ATA_MISCCTL_TIMORIDE , 1)
		*/
		writel(0x201, base + BK3710_MISCCTL);
		writel(0x001, base + BK3710_MISCCTL);

		/*
		* IORDYTMP IORDY Timer for Primary Register
		@@ -355,10 +323,9 @@ static int __init palm_bk3710_probe(struct platform_device *pdev)

		clk_enable(clk);
		rate = clk_get_rate(clk);
		ideclk_period = 1000000000UL / rate;

		/* Register the IDE interface with Linux ATA Interface */
		memset(&hw, 0, sizeof(hw));
		/* NOTE: round down to meet minimum timings; we count in clocks */
		ideclk_period = 1000000000UL / rate;

		mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		if (mem == NULL) {
		@@ -388,6 +355,7 @@ static int __init palm_bk3710_probe(struct platform_device *pdev)
		/* Configure the Palm Chip controller */
		palm_bk3710_chipinit(base);

		memset(&hw, 0, sizeof(hw));
		for (i = 0; i < IDE_NR_PORTS - 2; i++)
		hw.io_ports_array[i] = (unsigned long)
		(base + IDE_PALM_ATA_PRI_REG_OFFSET + i);
		@@ -400,6 +368,7 @@ static int __init palm_bk3710_probe(struct platform_device *pdev)
		palm_bk3710_port_info.udma_mask = rate < 100000000 ? ATA_UDMA4 :
		ATA_UDMA5;

		/* Register the IDE interface with Linux */
		rc = ide_host_add(&palm_bk3710_port_info, hws, NULL);
		if (rc)
		goto out;