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Commit b5fb0cc7 authored by Shaohui Xie's avatar Shaohui Xie Committed by Kumar Gala
Browse files

powerpc/fsl_rio: Fix non-standard HID1 register access 



Moved setting of RFXE bit so we get machine checks on RIO errors into
cpu_setup so that the RIO code isn't core specific.

Signed-off-by: default avatarShaohui Xie <b21989@freescale.com>
Cc: Li Yang <leoli@freescale.com>
Cc: Roy Zang <tie-fei.zang@freescale.com>
Cc: Alexandre Bounine <alexandre.bounine@idt.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 86985db6

arch/powerpc/kernel/cpu_setup_fsl_booke.S

+6 −0
Original line number Diff line number Diff line
@@ -64,6 +64,12 @@ _GLOBAL(__setup_cpu_e500v2) 
	bl	__e500_icache_setup

	bl	__e500_dcache_setup

	bl	__setup_e500_ivors

#ifdef CONFIG_RAPIDIO

	/* Ensure that RFXE is set */

	mfspr	r3,SPRN_HID1

	oris	r3,r3,HID1_RFXE@h

	mtspr	SPRN_HID1,r3

#endif

	mtlr	r4

	blr

_GLOBAL(__setup_cpu_e500mc)

arch/powerpc/sysdev/fsl_rio.c

+0 −2
Original line number Diff line number Diff line
@@ -1556,8 +1556,6 @@ int fsl_rio_setup(struct platform_device *dev) 
	saved_mcheck_exception = ppc_md.machine_check_exception;

	ppc_md.machine_check_exception = fsl_rio_mcheck_exception;

#endif

	/* Ensure that RFXE is set */

	mtspr(SPRN_HID1, (mfspr(SPRN_HID1) | 0x20000));



	return 0;

err: