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Commit b5d5b8f9 authored by Will Deacon's avatar Will Deacon
Browse files

ARM: hw_breakpoint: add initial Cortex-A15 (debug v7.1) support 



This patch adds initial support for Cortex-A15 (debug architecture v7.1)
to the hw_breakpoint ARM backend.

Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 90e93648

arch/arm/include/asm/hw_breakpoint.h

+1 −0
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ static inline void decode_ctrl_reg(u32 reg, 
#define ARM_DEBUG_ARCH_V6_1	2

#define ARM_DEBUG_ARCH_V7_ECP14	3

#define ARM_DEBUG_ARCH_V7_MM	4

#define ARM_DEBUG_ARCH_V7_1	5



/* Breakpoint */

#define ARM_BREAKPOINT_EXECUTE	0

arch/arm/kernel/hw_breakpoint.c

+36 −19
Original line number Diff line number Diff line
@@ -154,7 +154,10 @@ u8 arch_get_debug_arch(void) 
static int debug_arch_supported(void)

{

	u8 arch = get_debug_arch();

	return arch >= ARM_DEBUG_ARCH_V6 && arch <= ARM_DEBUG_ARCH_V7_ECP14;



	/* We don't support the memory-mapped interface. */

	return (arch >= ARM_DEBUG_ARCH_V6 && arch <= ARM_DEBUG_ARCH_V7_ECP14) ||

		arch >= ARM_DEBUG_ARCH_V7_1;

}



/* Determine number of BRP register available. */
@@ -255,6 +258,7 @@ static int enable_monitor_mode(void) 
		ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN));

		break;

	case ARM_DEBUG_ARCH_V7_ECP14:

	case ARM_DEBUG_ARCH_V7_1:

		ARM_DBG_WRITE(c2, 2, (dscr | ARM_DSCR_MDBGEN));

		break;

	default:
@@ -836,7 +840,7 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr, 
 */

static void reset_ctrl_regs(void *info)

{

	int i, cpu = smp_processor_id();

	int i, err = 0, cpu = smp_processor_id();

	u32 dbg_power;

	cpumask_t *cpumask = info;
@@ -848,13 +852,27 @@ static void reset_ctrl_regs(void *info) 
	 * Access Register to avoid taking undefined instruction exceptions

	 * later on.

	 */

	if (debug_arch >= ARM_DEBUG_ARCH_V7_ECP14) {

	switch (debug_arch) {

	case ARM_DEBUG_ARCH_V7_ECP14:

		/*

		 * Ensure sticky power-down is clear (i.e. debug logic is

		 * powered up).

		 */

		asm volatile("mrc p14, 0, %0, c1, c5, 4" : "=r" (dbg_power));

		if ((dbg_power & 0x1) == 0) {

		if ((dbg_power & 0x1) == 0)

			err = -EPERM;

		break;

	case ARM_DEBUG_ARCH_V7_1:

		/*

		 * Ensure the OS double lock is clear.

		 */

		asm volatile("mrc p14, 0, %0, c1, c3, 4" : "=r" (dbg_power));

		if ((dbg_power & 0x1) == 1)

			err = -EPERM;

		break;

	}



	if (err) {

		pr_warning("CPU %d debug is powered down!\n", cpu);

		cpumask_or(cpumask, cpumask, cpumask_of(cpu));

		return;
@@ -873,7 +891,6 @@ static void reset_ctrl_regs(void *info) 
	 */

	asm volatile("mcr p14, 0, %0, c0, c7, 0" : : "r" (0));

	isb();

	}



	if (enable_monitor_mode())

		return;