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Commit b5cfeed6 authored by Jingoo Han's avatar Jingoo Han Committed by Florian Tobias Schandinat
Browse files

video: exynos_dp: check DP PLL Lock status 



DP PLL Lock status should be checked in order to  prevent unlocked PLL.

Signed-off-by: default avatarJingoo Han <jg1.han@samsung.com>
Signed-off-by: default avatarFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>
parent 4e0dd49d

drivers/video/exynos/exynos_dp_reg.c

+12 −1
Original line number Diff line number Diff line
@@ -271,6 +271,7 @@ void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp, 
void exynos_dp_init_analog_func(struct exynos_dp_device *dp)

{

	u32 reg;

	int timeout_loop = 0;



	exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
@@ -282,9 +283,19 @@ void exynos_dp_init_analog_func(struct exynos_dp_device *dp) 
	writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);



	/* Power up PLL */

	if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED)

	if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {

		exynos_dp_set_pll_power_down(dp, 0);



		while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {

			timeout_loop++;

			if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {

				dev_err(dp->dev, "failed to get pll lock status\n");

				return;

			}

			usleep_range(10, 20);

		}

	}



	/* Enable Serdes FIFO function and Link symbol clock domain module */

	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);

	reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N