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Commit b59f7822 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-fixes-2014-12-11' of... 

Merge tag 'drm-intel-next-fixes-2014-12-11' of git://anongit.freedesktop.org/drm-intel into drm-next

Here's a batch of i915 fixes for 3.19.

* tag 'drm-intel-next-fixes-2014-12-11' of git://anongit.freedesktop.org/drm-intel:
  drm/i915: save/restore GMBUS freq across suspend/resume on gen4
  drm/i915: Remove '& 0xffff' from the mask given to WA_REG()
  drm/i915: Invert the mask and val arguments in wa_add() and WA_REG()
  drm/i915/bdw: Fix the write setting up the WIZ hashing mode
  drm/i915: Don't complain about stolen conflicts on gen3
  drm/i915: resume MST after reading back hw state
  drm/i915: Handle inaccurate time conversion issues
  drm/i915: compute wait_ioctl timeout correctly
  drm/i915: don't always do full mode sets when infoframes are enabled
parents f41c2581 9f49c376

drivers/gpu/drm/i915/i915_drv.c

+2 −1
Original line number Diff line number Diff line
@@ -706,11 +706,12 @@ static int i915_drm_resume(struct drm_device *dev) 
			dev_priv->display.hpd_irq_setup(dev);

		spin_unlock_irq(&dev_priv->irq_lock);



		intel_dp_mst_resume(dev);

		drm_modeset_lock_all(dev);

		intel_modeset_setup_hw_state(dev, true);

		drm_modeset_unlock_all(dev);



		intel_dp_mst_resume(dev);



		/*

		 * ... but also need to make sure that hotplug processing

		 * doesn't cause havoc. Like in the driver load code we don't

drivers/gpu/drm/i915/i915_drv.h

+6 −0
Original line number Diff line number Diff line
@@ -924,6 +924,7 @@ struct i915_suspend_saved_registers { 
	u32 savePIPEB_LINK_N1;

	u32 saveMCHBAR_RENDER_STANDBY;

	u32 savePCH_PORT_HOTPLUG;

	u16 saveGCDGMBUS;

};



struct vlv_s0ix_state {
@@ -3032,6 +3033,11 @@ static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) 
	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);

}



static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)

{

        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);

}



static inline unsigned long

timespec_to_jiffies_timeout(const struct timespec *value)

{

drivers/gpu/drm/i915/i915_gem.c

+12 −1
Original line number Diff line number Diff line
@@ -1227,7 +1227,8 @@ int __i915_wait_seqno(struct intel_engine_cs *ring, u32 seqno, 
	if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))

		return 0;



	timeout_expire = timeout ? jiffies + nsecs_to_jiffies((u64)*timeout) : 0;

	timeout_expire = timeout ?

		jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0;



	if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {

		gen6_rps_boost(dev_priv);
@@ -1303,6 +1304,16 @@ int __i915_wait_seqno(struct intel_engine_cs *ring, u32 seqno, 
		s64 tres = *timeout - (now - before);



		*timeout = tres < 0 ? 0 : tres;



		/*

		 * Apparently ktime isn't accurate enough and occasionally has a

		 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch

		 * things up to make the test happy. We allow up to 1 jiffy.

		 *

		 * This is a regrssion from the timespec->ktime conversion.

		 */

		if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)

			*timeout = 0;

	}



	return ret;

drivers/gpu/drm/i915/i915_gem_stolen.c

+5 −1
Original line number Diff line number Diff line
@@ -137,7 +137,11 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev) 
		r = devm_request_mem_region(dev->dev, base + 1,

					    dev_priv->gtt.stolen_size - 1,

					    "Graphics Stolen Memory");

		if (r == NULL) {

		/*

		 * GEN3 firmware likes to smash pci bridges into the stolen

		 * range. Apparently this works.

		 */

		if (r == NULL && !IS_GEN3(dev)) {

			DRM_ERROR("conflict detected with stolen region: [0x%08x - 0x%08x]\n",

				  base, base + (uint32_t)dev_priv->gtt.stolen_size);

			base = 0;

drivers/gpu/drm/i915/i915_reg.h

+15 −3
Original line number Diff line number Diff line
@@ -32,8 +32,19 @@ 
#define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \

			       (pipe) == PIPE_B ? (b) : (c))



#define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))

#define _MASKED_BIT_DISABLE(a) ((a) << 16)

#define _MASKED_FIELD(mask, value) ({					   \

	if (__builtin_constant_p(mask))					   \

		BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \

	if (__builtin_constant_p(value))				   \

		BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \

	if (__builtin_constant_p(mask) && __builtin_constant_p(value))	   \

		BUILD_BUG_ON_MSG((value) & ~(mask),			   \

				 "Incorrect value for mask");		   \

	(mask) << 16 | (value); })

#define _MASKED_BIT_ENABLE(a)	({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })

#define _MASKED_BIT_DISABLE(a)	(_MASKED_FIELD((a), 0))







/* PCI config space */
@@ -74,6 +85,7 @@ 
#define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)

#define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)

#define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)

#define GCDGMBUS 0xcc

#define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
@@ -1282,7 +1294,7 @@ enum punit_power_well { 
#define   GEN6_WIZ_HASHING_8x8				GEN6_WIZ_HASHING(0, 0)

#define   GEN6_WIZ_HASHING_8x4				GEN6_WIZ_HASHING(0, 1)

#define   GEN6_WIZ_HASHING_16x4				GEN6_WIZ_HASHING(1, 0)

#define   GEN6_WIZ_HASHING_MASK				(GEN6_WIZ_HASHING(1, 1) << 16)

#define   GEN6_WIZ_HASHING_MASK				GEN6_WIZ_HASHING(1, 1)

#define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE		(1 << 5)



#define GFX_MODE	0x02520