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Commit b4c6f99e authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/powerplay: fix mclk in high clock for baffin 



Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b2d96143

drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c

+4 −6
Original line number Diff line number Diff line
@@ -1377,13 +1377,14 @@ static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) 
		result = polaris10_populate_single_memory_level(hwmgr,

				dpm_table->mclk_table.dpm_levels[i].value,

				&levels[i]);

		if (i == dpm_table->mclk_table.count - 1) {

			levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;

			levels[i].EnabledForActivity = 1;

		}

		if (result)

			return result;

	}



	/* Only enable level 0 for now. */

	levels[0].EnabledForActivity = 1;



	/* in order to prevent MC activity from stutter mode to push DPM up.

	 * the UVD change complements this by putting the MCLK in

	 * a higher state by default such that we are not effected by
@@ -1396,9 +1397,6 @@ static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) 
			(uint8_t)dpm_table->mclk_table.count;

	data->dpm_level_enable_mask.mclk_dpm_enable_mask =

			phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);

	/* set highest level watermark to high */

	levels[dpm_table->mclk_table.count - 1].DisplayWatermark =

			PPSMC_DISPLAY_WATERMARK_HIGH;



	/* level count will send to smc once at init smc table and never change */

	result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,