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Commit b3beb167 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau: modify object accessors, offset in bytes rather than dwords 



Reviewed-by: default avatarFrancisco Jerez <currojerez@riseup.net>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 479dcaea

drivers/gpu/drm/nouveau/nouveau_drv.h

+3 −11
Original line number Diff line number Diff line
@@ -138,6 +138,7 @@ enum nouveau_flags { 
#define NVOBJ_FLAG_ZERO_FREE		(1 << 2)

#define NVOBJ_FLAG_FAKE			(1 << 3)

struct nouveau_gpuobj {

	struct drm_device *dev;

	struct list_head list;



	struct nouveau_channel *im_channel;
@@ -1291,17 +1292,8 @@ static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 
}



/* object access */

static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj,

				unsigned index)

{

	return nv_ri32(dev, obj->im_pramin->start + index * 4);

}



static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj,

				unsigned index, u32 val)

{

	nv_wi32(dev, obj->im_pramin->start + index * 4, val);

}

extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);

extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);



/*

 * Logging

drivers/gpu/drm/nouveau/nouveau_grctx.h

+1 −1
Original line number Diff line number Diff line
@@ -126,7 +126,7 @@ gr_def(struct nouveau_grctx *ctx, uint32_t reg, uint32_t val) 
	reg = (reg - 0x00400000) / 4;

	reg = (reg - ctx->ctxprog_reg) + ctx->ctxvals_base;



	nv_wo32(ctx->dev, ctx->data, reg, val);

	nv_wo32(ctx->data, reg * 4, val);

}

#endif

drivers/gpu/drm/nouveau/nouveau_mem.c

+7 −4
Original line number Diff line number Diff line
@@ -169,8 +169,9 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size, 
			virt  += (end - pte);



			while (pte < end) {

				nv_wo32(dev, pgt, pte++, offset_l);

				nv_wo32(dev, pgt, pte++, offset_h);

				nv_wo32(pgt, (pte * 4) + 0, offset_l);

				nv_wo32(pgt, (pte * 4) + 4, offset_h);

				pte += 2;

			}

		}

	}
@@ -203,8 +204,10 @@ nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size) 
		pages -= (end - pte);

		virt  += (end - pte) << 15;



		while (pte < end)

			nv_wo32(dev, pgt, pte++, 0);

		while (pte < end) {

			nv_wo32(pgt, (pte * 4), 0);

			pte++;

		}

	}

	dev_priv->engine.instmem.flush(dev);

drivers/gpu/drm/nouveau/nouveau_object.c

+53 −39
Original line number Diff line number Diff line
@@ -88,6 +88,7 @@ nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan, 
	if (!gpuobj)

		return -ENOMEM;

	NV_DEBUG(dev, "gpuobj %p\n", gpuobj);

	gpuobj->dev = dev;

	gpuobj->flags = flags;

	gpuobj->im_channel = chan;
@@ -134,7 +135,7 @@ nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan, 
		int i;



		for (i = 0; i < gpuobj->im_pramin->size; i += 4)

			nv_wo32(dev, gpuobj, i/4, 0);

			nv_wo32(gpuobj, i, 0);

		engine->instmem.flush(dev);

	}
@@ -224,7 +225,7 @@ nouveau_gpuobj_del(struct drm_device *dev, struct nouveau_gpuobj **pgpuobj) 


	if (gpuobj->im_pramin && (gpuobj->flags & NVOBJ_FLAG_ZERO_FREE)) {

		for (i = 0; i < gpuobj->im_pramin->size; i += 4)

			nv_wo32(dev, gpuobj, i/4, 0);

			nv_wo32(gpuobj, i, 0);

		engine->instmem.flush(dev);

	}
@@ -435,6 +436,7 @@ nouveau_gpuobj_new_fake(struct drm_device *dev, uint32_t p_offset, 
	if (!gpuobj)

		return -ENOMEM;

	NV_DEBUG(dev, "gpuobj %p\n", gpuobj);

	gpuobj->dev = dev;

	gpuobj->im_channel = NULL;

	gpuobj->flags      = flags | NVOBJ_FLAG_FAKE;
@@ -458,7 +460,7 @@ nouveau_gpuobj_new_fake(struct drm_device *dev, uint32_t p_offset, 


	if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {

		for (i = 0; i < gpuobj->im_pramin->size; i += 4)

			nv_wo32(dev, gpuobj, i/4, 0);

			nv_wo32(gpuobj, i, 0);

		dev_priv->engine.instmem.flush(dev);

	}
@@ -555,14 +557,12 @@ nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class, 
		adjust = offset &  0x00000fff;

		frame  = offset & ~0x00000fff;



		nv_wo32(dev, *gpuobj, 0, ((1<<12) | (1<<13) |

				(adjust << 20) |

				 (access << 14) |

				 (target << 16) |

		nv_wo32(*gpuobj,  0, ((1<<12) | (1<<13) | (adjust << 20) |

				      (access << 14) | (target << 16) |

				      class));

		nv_wo32(dev, *gpuobj, 1, size - 1);

		nv_wo32(dev, *gpuobj, 2, frame | pte_flags);

		nv_wo32(dev, *gpuobj, 3, frame | pte_flags);

		nv_wo32(*gpuobj,  4, size - 1);

		nv_wo32(*gpuobj,  8, frame | pte_flags);

		nv_wo32(*gpuobj, 12, frame | pte_flags);

	} else {

		uint64_t limit = offset + size - 1;

		uint32_t flags0, flags5;
@@ -575,12 +575,12 @@ nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class, 
			flags5 = 0x00080000;

		}



		nv_wo32(dev, *gpuobj, 0, flags0 | class);

		nv_wo32(dev, *gpuobj, 1, lower_32_bits(limit));

		nv_wo32(dev, *gpuobj, 2, lower_32_bits(offset));

		nv_wo32(dev, *gpuobj, 3, ((upper_32_bits(limit) & 0xff) << 24) |

		nv_wo32(*gpuobj,  0, flags0 | class);

		nv_wo32(*gpuobj,  4, lower_32_bits(limit));

		nv_wo32(*gpuobj,  8, lower_32_bits(offset));

		nv_wo32(*gpuobj, 12, ((upper_32_bits(limit) & 0xff) << 24) |

				      (upper_32_bits(offset) & 0xff));

		nv_wo32(dev, *gpuobj, 5, flags5);

		nv_wo32(*gpuobj, 20, flags5);

	}



	instmem->flush(dev);
@@ -699,25 +699,25 @@ nouveau_gpuobj_gr_new(struct nouveau_channel *chan, int class, 
	}



	if (dev_priv->card_type >= NV_50) {

		nv_wo32(dev, *gpuobj, 0, class);

		nv_wo32(dev, *gpuobj, 5, 0x00010000);

		nv_wo32(*gpuobj,  0, class);

		nv_wo32(*gpuobj, 20, 0x00010000);

	} else {

		switch (class) {

		case NV_CLASS_NULL:

			nv_wo32(dev, *gpuobj, 0, 0x00001030);

			nv_wo32(dev, *gpuobj, 1, 0xFFFFFFFF);

			nv_wo32(*gpuobj, 0, 0x00001030);

			nv_wo32(*gpuobj, 4, 0xFFFFFFFF);

			break;

		default:

			if (dev_priv->card_type >= NV_40) {

				nv_wo32(dev, *gpuobj, 0, class);

				nv_wo32(*gpuobj, 0, class);

#ifdef __BIG_ENDIAN

				nv_wo32(dev, *gpuobj, 2, 0x01000000);

				nv_wo32(*gpuobj, 8, 0x01000000);

#endif

			} else {

#ifdef __BIG_ENDIAN

				nv_wo32(dev, *gpuobj, 0, class | 0x00080000);

				nv_wo32(*gpuobj, 0, class | 0x00080000);

#else

				nv_wo32(dev, *gpuobj, 0, class);

				nv_wo32(*gpuobj, 0, class);

#endif

			}

		}
@@ -836,21 +836,20 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan, 
		if (ret)

			return ret;

		for (i = 0; i < 0x4000; i += 8) {

			nv_wo32(dev, chan->vm_pd, (i+0)/4, 0x00000000);

			nv_wo32(dev, chan->vm_pd, (i+4)/4, 0xdeadcafe);

			nv_wo32(chan->vm_pd, i + 0, 0x00000000);

			nv_wo32(chan->vm_pd, i + 4, 0xdeadcafe);

		}



		pde = (dev_priv->vm_gart_base / (512*1024*1024)) * 2;

		pde = (dev_priv->vm_gart_base / (512*1024*1024)) * 8;

		ret = nouveau_gpuobj_ref_add(dev, NULL, 0,

					     dev_priv->gart_info.sg_ctxdma,

					     &chan->vm_gart_pt);

		if (ret)

			return ret;

		nv_wo32(dev, chan->vm_pd, pde++,

			    chan->vm_gart_pt->instance | 0x03);

		nv_wo32(dev, chan->vm_pd, pde++, 0x00000000);

		nv_wo32(chan->vm_pd, pde + 0, chan->vm_gart_pt->instance | 3);

		nv_wo32(chan->vm_pd, pde + 4, 0x00000000);



		pde = (dev_priv->vm_vram_base / (512*1024*1024)) * 2;

		pde = (dev_priv->vm_vram_base / (512*1024*1024)) * 8;

		for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) {

			ret = nouveau_gpuobj_ref_add(dev, NULL, 0,

						     dev_priv->vm_vram_pt[i],
@@ -858,9 +857,10 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan, 
			if (ret)

				return ret;



			nv_wo32(dev, chan->vm_pd, pde++,

			nv_wo32(chan->vm_pd, pde + 0,

				chan->vm_vram_pt[i]->instance | 0x61);

			nv_wo32(dev, chan->vm_pd, pde++, 0x00000000);

			nv_wo32(chan->vm_pd, pde + 4, 0x00000000);

			pde += 8;

		}



		instmem->flush(dev);
@@ -996,8 +996,8 @@ nouveau_gpuobj_suspend(struct drm_device *dev) 
			return -ENOMEM;

		}



		for (i = 0; i < gpuobj->im_pramin->size / 4; i++)

			gpuobj->im_backing_suspend[i] = nv_ro32(dev, gpuobj, i);

		for (i = 0; i < gpuobj->im_pramin->size; i += 4)

			gpuobj->im_backing_suspend[i/4] = nv_ro32(gpuobj, i);

	}



	return 0;
@@ -1042,8 +1042,8 @@ nouveau_gpuobj_resume(struct drm_device *dev) 
		if (!gpuobj->im_backing_suspend)

			continue;



		for (i = 0; i < gpuobj->im_pramin->size / 4; i++)

			nv_wo32(dev, gpuobj, i, gpuobj->im_backing_suspend[i]);

		for (i = 0; i < gpuobj->im_pramin->size; i += 4)

			nv_wo32(gpuobj, i, gpuobj->im_backing_suspend[i/4]);

		dev_priv->engine.instmem.flush(dev);

	}
@@ -1120,3 +1120,17 @@ int nouveau_ioctl_gpuobj_free(struct drm_device *dev, void *data, 


	return 0;

}



u32

nv_ro32(struct nouveau_gpuobj *gpuobj, u32 offset)

{

	struct drm_device *dev = gpuobj->dev;

	return nv_ri32(dev, gpuobj->im_pramin->start + offset);

}



void

nv_wo32(struct nouveau_gpuobj *gpuobj, u32 offset, u32 val)

{

	struct drm_device *dev = gpuobj->dev;

	nv_wi32(dev, gpuobj->im_pramin->start + offset, val);

}

drivers/gpu/drm/nouveau/nouveau_ramht.c

+8 −8
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ nouveau_ramht_entry_valid(struct drm_device *dev, struct nouveau_gpuobj *ramht, 
			  uint32_t offset)

{

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	uint32_t ctx = nv_ro32(dev, ramht, (offset + 4)/4);

	uint32_t ctx = nv_ro32(ramht, offset + 4);



	if (dev_priv->card_type < NV_40)

		return ((ctx & NV_RAMHT_CONTEXT_VALID) != 0);
@@ -100,15 +100,15 @@ nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) 
			NV_DEBUG(dev,

				 "insert ch%d 0x%08x: h=0x%08x, c=0x%08x\n",

				 chan->id, co, ref->handle, ctx);

			nv_wo32(dev, ramht, (co + 0)/4, ref->handle);

			nv_wo32(dev, ramht, (co + 4)/4, ctx);

			nv_wo32(ramht, co + 0, ref->handle);

			nv_wo32(ramht, co + 4, ctx);



			list_add_tail(&ref->list, &chan->ramht_refs);

			instmem->flush(dev);

			return 0;

		}

		NV_DEBUG(dev, "collision ch%d 0x%08x: h=0x%08x\n",

			 chan->id, co, nv_ro32(dev, ramht, co/4));

			 chan->id, co, nv_ro32(ramht, co));



		co += 8;

		if (co >= dev_priv->ramht_size)
@@ -136,13 +136,13 @@ nouveau_ramht_remove(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) 
	co = ho = nouveau_ramht_hash_handle(dev, chan->id, ref->handle);

	do {

		if (nouveau_ramht_entry_valid(dev, ramht, co) &&

		    (ref->handle == nv_ro32(dev, ramht, (co/4)))) {

		    (ref->handle == nv_ro32(ramht, co))) {

			NV_DEBUG(dev,

				 "remove ch%d 0x%08x: h=0x%08x, c=0x%08x\n",

				 chan->id, co, ref->handle,

				 nv_ro32(dev, ramht, (co + 4)));

			nv_wo32(dev, ramht, (co + 0)/4, 0x00000000);

			nv_wo32(dev, ramht, (co + 4)/4, 0x00000000);

				 nv_ro32(ramht, co + 4));

			nv_wo32(ramht, co + 0, 0x00000000);

			nv_wo32(ramht, co + 4, 0x00000000);



			list_del(&ref->list);

			instmem->flush(dev);