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Commit b3205dea authored by Sachin Kamat's avatar Sachin Kamat Committed by Kukjin Kim
Browse files

ARM: EXYNOS: Map SYSRAM through generic DT bindings 



Instead of hardcoding the SYSRAM details for each SoC,
pass this information through device tree (DT) and make
the code SoC agnostic. Generic DT SRAM bindings are
used for achieving this.

Signed-off-by: default avatarSachin Kamat <sachin.kamat@linaro.org>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Acked-by: default avatarHeiko Stuebner <heiko@sntech.de>
Reviewed-by: default avatarTomasz Figa <t.figa@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 3528dd34

arch/arm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -843,6 +843,7 @@ config ARCH_EXYNOS 
	select HAVE_S3C_RTC if RTC_CLASS

	select NEED_MACH_MEMORY_H

	select SPARSE_IRQ

	select SRAM

	select USE_OF

	help

	  Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)

arch/arm/boot/dts/exynos4210-universal_c210.dts

+15 −0
Original line number Diff line number Diff line
@@ -28,6 +28,21 @@ 
		bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1";

	};



	sysram@02020000 {

		smp-sysram@0 {

			status = "disabled";

		};



		smp-sysram@5000 {

			compatible = "samsung,exynos4210-sysram";

			reg = <0x5000 0x1000>;

		};



		smp-sysram@1f000 {

			status = "disabled";

		};

	};



	mct@10050000 {

		compatible = "none";

	};

arch/arm/boot/dts/exynos4210.dtsi

+18 −0
Original line number Diff line number Diff line
@@ -31,6 +31,24 @@ 
		pinctrl2 = &pinctrl_2;

	};



	sysram@02020000 {

		compatible = "mmio-sram";

		reg = <0x02020000 0x20000>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0x02020000 0x20000>;



		smp-sysram@0 {

			compatible = "samsung,exynos4210-sysram";

			reg = <0x0 0x1000>;

		};



		smp-sysram@1f000 {

			compatible = "samsung,exynos4210-sysram-ns";

			reg = <0x1f000 0x1000>;

		};

	};



	pd_lcd1: lcd1-power-domain@10023CA0 {

		compatible = "samsung,exynos4210-pd";

		reg = <0x10023CA0 0x20>;

arch/arm/boot/dts/exynos4x12.dtsi

+18 −0
Original line number Diff line number Diff line
@@ -37,6 +37,24 @@ 
		interrupts = <2 2>, <3 2>, <18 2>, <19 2>;

	};



	sysram@02020000 {

		compatible = "mmio-sram";

		reg = <0x02020000 0x40000>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0x02020000 0x40000>;



		smp-sysram@0 {

			compatible = "samsung,exynos4210-sysram";

			reg = <0x0 0x1000>;

		};



		smp-sysram@2f000 {

			compatible = "samsung,exynos4210-sysram-ns";

			reg = <0x2f000 0x1000>;

		};

	};



	pd_isp: isp-power-domain@10023CA0 {

		compatible = "samsung,exynos4210-pd";

		reg = <0x10023CA0 0x20>;

arch/arm/boot/dts/exynos5250.dtsi

+18 −0
Original line number Diff line number Diff line
@@ -72,6 +72,24 @@ 
		};

	};



	sysram@02020000 {

		compatible = "mmio-sram";

		reg = <0x02020000 0x30000>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0x02020000 0x30000>;



		smp-sysram@0 {

			compatible = "samsung,exynos4210-sysram";

			reg = <0x0 0x1000>;

		};



		smp-sysram@2f000 {

			compatible = "samsung,exynos4210-sysram-ns";

			reg = <0x2f000 0x1000>;

		};

	};



	pd_gsc: gsc-power-domain@10044000 {

		compatible = "samsung,exynos4210-pd";

		reg = <0x10044000 0x20>;