Commit b2a3c5be authored Jan 22, 2016 by James Hogan Committed by Ralf Baechle May 09, 2016

MIPS: c-r4k: Sync icache when it fills from dcache



It is still necessary to handle icache coherency in flush_cache_range()
and copy_to_user_page() when the icache fills from the dcache, even
though the dcache does not need to be written back. However when this
handling was added in commit 2eaa7ec2 ("[MIPS] Handle I-cache
coherency in flush_cache_range()"), it did not do any icache flushing
when it fills from dcache.

Therefore fix r4k_flush_cache_range() to run
local_r4k_flush_cache_range() without taking into account whether icache
fills from dcache, so that the icache coherency gets handled. Checks are
also added in local_r4k_flush_cache_range() so that the dcache blast
doesn't take place when icache fills from dcache.

A test to mmap a page PROT_READ|PROT_WRITE, modify code in it, and
mprotect it to VM_READ|VM_EXEC (similar to case described in above
commit) can hit this case quite easily to verify the fix.

A similar check was added in commit f8829cae ("[MIPS] Fix aliasing
bug in copy_to_user_page / copy_from_user_page"), so also fix
copy_to_user_page() similarly, to call flush_cache_page() without taking
into account whether icache fills from dcache, since flush_cache_page()
already takes that into account to avoid performing a dcache flush.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com>
Cc: Manuel Lauss <manuel.lauss@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12179/


Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 679eb637

arch/mips/mm/c-r4k.c

+9 −2

Original line number	Diff line number	Diff line
		@@ -492,7 +492,14 @@ static inline void local_r4k_flush_cache_range(void * args)
		if (!(has_valid_asid(vma->vm_mm)))
		return;

		/*
		* If dcache can alias, we must blast it since mapping is changing.
		* If executable, we must ensure any dirty lines are written back far
		* enough to be visible to icache.
		*/
		if (cpu_has_dc_aliases \|\| (exec && !cpu_has_ic_fills_f_dc))
		r4k_blast_dcache();
		/* If executable, blast stale lines from icache */
		if (exec)
		r4k_blast_icache();
		}
		@@ -502,7 +509,7 @@ static void r4k_flush_cache_range(struct vm_area_struct *vma,
		{
		int exec = vma->vm_flags & VM_EXEC;

		if (cpu_has_dc_aliases \|\| (exec && !cpu_has_ic_fills_f_dc))
		if (cpu_has_dc_aliases \|\| exec)
		r4k_on_each_cpu(local_r4k_flush_cache_range, vma);
		}

arch/mips/mm/init.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -196,7 +196,7 @@ void copy_to_user_page(struct vm_area_struct *vma,
		if (cpu_has_dc_aliases)
		SetPageDcacheDirty(page);
		}
		if ((vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc)
		if (vma->vm_flags & VM_EXEC)
		flush_cache_page(vma, vaddr, page_to_pfn(page));
		}