Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b1f60b70 authored by Zhenyu Wang's avatar Zhenyu Wang Committed by Eric Anholt
Browse files

drm/i915: fix panel fitting filter coefficient select for Ironlake 



Must set filter selection as hardcoded coefficients for medium 3x3
filtering, which matches vbios setting for Ironlake.

This fixes display corrupt issue on HP arrandale with new vbios.

Cc: Stable Team <stable@kernel.org>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent c038e51e

drivers/gpu/drm/i915/i915_reg.h

+5 −0
Original line number Diff line number Diff line
@@ -2039,6 +2039,11 @@ 
#define PFA_CTL_1               0x68080

#define PFB_CTL_1               0x68880

#define  PF_ENABLE              (1<<31)

#define  PF_FILTER_MASK		(3<<23)

#define  PF_FILTER_PROGRAMMED	(0<<23)

#define  PF_FILTER_MED_3x3	(1<<23)

#define  PF_FILTER_EDGE_ENHANCE	(2<<23)

#define  PF_FILTER_EDGE_SOFTEN	(3<<23)

#define PFA_WIN_SZ		0x68074

#define PFB_WIN_SZ		0x68874

#define PFA_WIN_POS		0x68070

drivers/gpu/drm/i915/intel_display.c

+1 −1
Original line number Diff line number Diff line
@@ -1515,7 +1515,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode) 
		/* Enable panel fitting for LVDS */

		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {

			temp = I915_READ(pf_ctl_reg);

			I915_WRITE(pf_ctl_reg, temp | PF_ENABLE);

			I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);



			/* currently full aspect */

			I915_WRITE(pf_win_pos, 0);