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Commit b1ab1b4d authored by Borislav Petkov's avatar Borislav Petkov Committed by H. Peter Anvin
Browse files

x86, cacheinfo: Unify AMD L3 cache index disable checking 



All F10h CPUs starting with model 8 resp. 9, stepping 1, support L3
cache index disable. Concentrate the family, model, stepping checking at
one place and enable the feature implicitly on upcoming Fam10h models.

Signed-off-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
LKML-Reference: <1271945222-5283-2-git-send-email-bp@amd64.org>
Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
parent 6dad2a29

arch/x86/kernel/cpu/intel_cacheinfo.c

+10 −7
Original line number Diff line number Diff line
@@ -328,16 +328,20 @@ static unsigned int __cpuinit amd_calc_l3_indices(void) 
static void __cpuinit

amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)

{

	if (index < 3)

	if (boot_cpu_data.x86 != 0x10)

		return;



	if (boot_cpu_data.x86 == 0x11)

	if (index < 3)

		return;



	/* see errata #382 and #388 */

	if ((boot_cpu_data.x86 == 0x10) &&

	    ((boot_cpu_data.x86_model < 0x8) ||

	     (boot_cpu_data.x86_mask  < 0x1)))

	if (boot_cpu_data.x86_model < 0x8)

		return;



	if ((boot_cpu_data.x86_model == 0x8 ||

	     boot_cpu_data.x86_model == 0x9)

		&&

	     boot_cpu_data.x86_mask < 0x1)

			return;



	this_leaf->can_disable = true;
@@ -443,7 +447,6 @@ __cpuinit cpuid4_cache_lookup_regs(int index, 


	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {

		amd_cpuid4(index, &eax, &ebx, &ecx);

		if (boot_cpu_data.x86 >= 0x10)

		amd_check_l3_disable(index, this_leaf);

	} else {

		cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);