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Commit b10690d1 authored by Vladimir Barinov's avatar Vladimir Barinov Committed by Simon Horman
Browse files

arm64: dts: h3ulcb: initial device tree 



Add the initial device tree for the R8A7795 SoC based H3ULCB low cost
board.

This commit supports the following peripherals:
- SCIF (console)

Signed-off-by: default avatarVladimir Barinov <vladimir.barinov@cogentembedded.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent f1d404fa

arch/arm64/boot/dts/renesas/Makefile

+1 −1
Original line number Diff line number Diff line 
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb

dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb

dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb



always		:= $(dtb-y)

arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts

0 → 100644
+51 −0
Original line number Diff line number Diff line 
/*

 * Device Tree Source for the H3ULCB board

 *

 * Copyright (C) 2016 Renesas Electronics Corp.

 * Copyright (C) 2016 Cogent Embedded, Inc.

 *

 * This file is licensed under the terms of the GNU General Public License

 * version 2.  This program is licensed "as is" without any warranty of any

 * kind, whether express or implied.

 */



/dts-v1/;

#include "r8a7795.dtsi"

#include <dt-bindings/gpio/gpio.h>



/ {

	model = "Renesas H3ULCB board based on r8a7795";

	compatible = "renesas,h3ulcb", "renesas,r8a7795";



	aliases {

		serial0 = &scif2;

	};



	chosen {

		stdout-path = "serial0:115200n8";

	};



	memory@48000000 {

		device_type = "memory";

		/* first 128MB is reserved for secure area. */

		reg = <0x0 0x48000000 0x0 0x38000000>;

	};

};



&extal_clk {

	clock-frequency = <16666666>;

};



&pfc {

	scif2_pins: scif2 {

		groups = "scif2_data_a";

		function = "scif2";

	};

};



&scif2 {

	pinctrl-0 = <&scif2_pins>;

	pinctrl-names = "default";



	status = "okay";

};