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Commit b0da12d5 authored by Stephen Warren's avatar Stephen Warren
Browse files

ARM: tegra: add PCIe-related pins to the Jetson TK1 pinmux tables 



This pinmux tables currently omit any configuration for PCIe clk_req,
wake, and rst pins, which in turn causes intermittent failures in
U-Boot's PCIe support. Import an updated version of the pinmux tables
which rectifies this.

(While I'm still hoping to remove the pinmux tables from DTs for
Tegra124+ devices, while they're still here, they may as well be
complete and correct).

Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent 1b3ce99f

arch/arm/boot/dts/tegra124-jetson-tk1.dts

+35 −0
Original line number Diff line number Diff line
@@ -1231,6 +1231,41 @@ 
				nvidia,tristate = <TEGRA_PIN_DISABLE>;

				nvidia,enable-input = <TEGRA_PIN_DISABLE>;

			};

			pex_l0_rst_n_pdd1 {

				nvidia,pins = "pex_l0_rst_n_pdd1";

				nvidia,function = "pe0";

				nvidia,pull = <TEGRA_PIN_PULL_NONE>;

				nvidia,tristate = <TEGRA_PIN_DISABLE>;

				nvidia,enable-input = <TEGRA_PIN_DISABLE>;

			};

			pex_l0_clkreq_n_pdd2 {

				nvidia,pins = "pex_l0_clkreq_n_pdd2";

				nvidia,function = "pe0";

				nvidia,pull = <TEGRA_PIN_PULL_UP>;

				nvidia,tristate = <TEGRA_PIN_DISABLE>;

				nvidia,enable-input = <TEGRA_PIN_ENABLE>;

			};

			pex_wake_n_pdd3 {

				nvidia,pins = "pex_wake_n_pdd3";

				nvidia,function = "pe";

				nvidia,pull = <TEGRA_PIN_PULL_UP>;

				nvidia,tristate = <TEGRA_PIN_DISABLE>;

				nvidia,enable-input = <TEGRA_PIN_ENABLE>;

			};

			pex_l1_rst_n_pdd5 {

				nvidia,pins = "pex_l1_rst_n_pdd5";

				nvidia,function = "pe1";

				nvidia,pull = <TEGRA_PIN_PULL_NONE>;

				nvidia,tristate = <TEGRA_PIN_DISABLE>;

				nvidia,enable-input = <TEGRA_PIN_DISABLE>;

			};

			pex_l1_clkreq_n_pdd6 {

				nvidia,pins = "pex_l1_clkreq_n_pdd6";

				nvidia,function = "pe1";

				nvidia,pull = <TEGRA_PIN_PULL_UP>;

				nvidia,tristate = <TEGRA_PIN_DISABLE>;

				nvidia,enable-input = <TEGRA_PIN_ENABLE>;

			};

			clk3_out_pee0 {

				nvidia,pins = "clk3_out_pee0";

				nvidia,function = "extperiph3";