Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b0ce4bd5 authored by Leonid Yegoshin's avatar Leonid Yegoshin Committed by Markos Chandras
Browse files

MIPS: lib: memcpy: Add MIPS R6 support



MIPS R6 does not support the unaligned load and store instructions
so we add a special MIPS R6 case to copy one byte at a time if we
need to read/write to unaligned memory addresses.

Signed-off-by: default avatarLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
parent fee313d4
Loading
Loading
Loading
Loading
+23 −0
Original line number Diff line number Diff line
@@ -293,9 +293,14 @@
	 and	t0, src, ADDRMASK
	PREFS(	0, 2*32(src) )
	PREFD(	1, 2*32(dst) )
#ifndef CONFIG_CPU_MIPSR6
	bnez	t1, .Ldst_unaligned\@
	 nop
	bnez	t0, .Lsrc_unaligned_dst_aligned\@
#else
	or	t0, t0, t1
	bnez	t0, .Lcopy_unaligned_bytes\@
#endif
	/*
	 * use delay slot for fall-through
	 * src and dst are aligned; need to compute rem
@@ -376,6 +381,7 @@
	bne	rem, len, 1b
	.set	noreorder

#ifndef CONFIG_CPU_MIPSR6
	/*
	 * src and dst are aligned, need to copy rem bytes (rem < NBYTES)
	 * A loop would do only a byte at a time with possible branch
@@ -477,6 +483,7 @@
	bne	len, rem, 1b
	.set	noreorder

#endif /* !CONFIG_CPU_MIPSR6 */
.Lcopy_bytes_checklen\@:
	beqz	len, .Ldone\@
	 nop
@@ -504,6 +511,22 @@
.Ldone\@:
	jr	ra
	 nop

#ifdef CONFIG_CPU_MIPSR6
.Lcopy_unaligned_bytes\@:
1:
	COPY_BYTE(0)
	COPY_BYTE(1)
	COPY_BYTE(2)
	COPY_BYTE(3)
	COPY_BYTE(4)
	COPY_BYTE(5)
	COPY_BYTE(6)
	COPY_BYTE(7)
	ADD	src, src, 8
	b	1b
	 ADD	dst, dst, 8
#endif /* CONFIG_CPU_MIPSR6 */
	.if __memcpy == 1
	END(memcpy)
	.set __memcpy, 0