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Commit b0cc6020 authored by Yijing Wang's avatar Yijing Wang Committed by Bjorn Helgaas
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PCI: Enable ARI if dev and upstream bridge support it; disable otherwise



Currently, we enable ARI in a device's upstream bridge if the bridge and
the device support it.  But we never disable ARI, even if the device is
removed and replaced with a device that doesn't support ARI.

This means that if we hot-remove an ARI device and replace it with a
non-ARI multi-function device, we find only function 0 of the new device
because the upstream bridge still has ARI enabled, and next_ari_fn()
only returns function 0 for the new non-ARI device.

This patch disables ARI in the upstream bridge if the device doesn't
support ARI.  See the PCIe spec, r3.0, sec 6.13.

[bhelgaas: changelog, function comment]
Signed-off-by: default avatarYijing Wang <wangyijing@huawei.com>
Signed-off-by: default avatarJiang Liu <jiang.liu@huawei.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent d1c3ed66
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+12 −5
Original line number Diff line number Diff line
@@ -2069,6 +2069,9 @@ void pci_free_cap_save_buffers(struct pci_dev *dev)
/**
 * pci_enable_ari - enable ARI forwarding if hardware support it
 * @dev: the PCI device
 *
 * If @dev and its upstream bridge both support ARI, enable ARI in the
 * bridge.  Otherwise, disable ARI in the bridge.
 */
void pci_enable_ari(struct pci_dev *dev)
{
@@ -2078,9 +2081,6 @@ void pci_enable_ari(struct pci_dev *dev)
	if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
		return;

	if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI))
		return;

	bridge = dev->bus->self;
	if (!bridge)
		return;
@@ -2089,8 +2089,15 @@ void pci_enable_ari(struct pci_dev *dev)
	if (!(cap & PCI_EXP_DEVCAP2_ARI))
		return;

	pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_ARI);
	if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
		pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
					 PCI_EXP_DEVCTL2_ARI);
		bridge->ari_enabled = 1;
	} else {
		pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
					   PCI_EXP_DEVCTL2_ARI);
		bridge->ari_enabled = 0;
	}
}

/**