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Commit b03bb79d authored by Thierry Reding's avatar Thierry Reding
Browse files

Merge tag 'tegra-for-3.14-dmas-resets-rework' into drm/for-next 

ARM: tegra: implement common DMA and resets DT bindings

This series converts the Tegra DTs and drivers to use the common/
standard DMA and reset bindings, rather than custom bindings. It also
adds complete documentation for the Tegra clock bindings without
actually changing any binding definitions.

This conversion relies on a few sets of patches in branches from outside
the Tegra tree:

1) A patch to add an DMA channel request API which allows deferred probe
   to be implemented.

2) A patch to implement a common part of the of_xlate function for DMA
   controllers.

3) Some ASoC patches (which in turn rely on (1) above), which support
   deferred probe during DMA channel allocation.

4) The Tegra clock driver changes for 3.14.

Consequently, this branch is based on a merge of all of those external
branches.

In turn, this branch is or will be pulled into a few places that either
rely on features introduced here, or would otherwise conflict with the
patches:

a) Tegra's own for-3.14/powergate and for-4.14/dt branches, to avoid
   conflicts.

b) The DRM tree, which introduces new code that relies on the reset
   controller framework introduced in this branch, and to avoid
   conflicts.
parents 319e2e3f 8a0a1af3

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt

+1 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ Required properties: 
- compatible : Should contain "nvidia,tegra<chip>-pmc".

- reg : Offset and length of the register set for the device

- clocks : Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names : Must include the following entries:

  "pclk" (The Tegra clock of that name),

  "clk32k_in" (The 32KHz clock input to Tegra).

Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt

+4 −0
Original line number Diff line number Diff line
@@ -15,6 +15,9 @@ Required properties : 
  In clock consumers, this cell represents the clock ID exposed by the

  CAR. The assignments may be found in header file

  <dt-bindings/clock/tegra114-car.h>.

- #reset-cells : Should be 1.

  In clock consumers, this cell represents the bit number in the CAR's

  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.



Example SoC include file:
@@ -23,6 +26,7 @@ Example SoC include file: 
		compatible = "nvidia,tegra114-car";

		reg = <0x60006000 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	usb@c5004000 {

Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt

0 → 100644
+63 −0
Original line number Diff line number Diff line 
NVIDIA Tegra124 Clock And Reset Controller



This binding uses the common clock binding:

Documentation/devicetree/bindings/clock/clock-bindings.txt



The CAR (Clock And Reset) Controller on Tegra is the HW module responsible

for muxing and gating Tegra's clocks, and setting their rates.



Required properties :

- compatible : Should be "nvidia,tegra124-car"

- reg : Should contain CAR registers location and length

- clocks : Should contain phandle and clock specifiers for two clocks:

  the 32 KHz "32k_in", and the board-specific oscillator "osc".

- #clock-cells : Should be 1.

  In clock consumers, this cell represents the clock ID exposed by the

  CAR. The assignments may be found in header file

  <dt-bindings/clock/tegra124-car.h>.

- #reset-cells : Should be 1.

  In clock consumers, this cell represents the bit number in the CAR's

  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.



Example SoC include file:



/ {

	tegra_car: clock {

		compatible = "nvidia,tegra124-car";

		reg = <0x60006000 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	usb@c5004000 {

		clocks = <&tegra_car TEGRA124_CLK_USB2>;

	};

};



Example board file:



/ {

	clocks {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <0>;



		osc: clock@0 {

			compatible = "fixed-clock";

			reg = <0>;

			#clock-cells = <0>;

			clock-frequency = <112400000>;

		};



		clk_32k: clock@1 {

			compatible = "fixed-clock";

			reg = <1>;

			#clock-cells = <0>;

			clock-frequency = <32768>;

		};

	};



	&tegra_car {

		clocks = <&clk_32k> <&osc>;

	};

};

Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt

+4 −0
Original line number Diff line number Diff line
@@ -15,6 +15,9 @@ Required properties : 
  In clock consumers, this cell represents the clock ID exposed by the

  CAR. The assignments may be found in header file

  <dt-bindings/clock/tegra20-car.h>.

- #reset-cells : Should be 1.

  In clock consumers, this cell represents the bit number in the CAR's

  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.



Example SoC include file:
@@ -23,6 +26,7 @@ Example SoC include file: 
		compatible = "nvidia,tegra20-car";

		reg = <0x60006000 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	usb@c5004000 {

Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt

+4 −0
Original line number Diff line number Diff line
@@ -15,6 +15,9 @@ Required properties : 
  In clock consumers, this cell represents the clock ID exposed by the

  CAR. The assignments may be found in header file

  <dt-bindings/clock/tegra30-car.h>.

- #reset-cells : Should be 1.

  In clock consumers, this cell represents the bit number in the CAR's

  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.



Example SoC include file:
@@ -23,6 +26,7 @@ Example SoC include file: 
		compatible = "nvidia,tegra30-car";

		reg = <0x60006000 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	usb@c5004000 {