Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit affe8a2a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'for-linus-20160801' of git://git.infradead.org/linux-mtd 

Pull MTD updates from Brian Norris:
 "NAND:

    Quoting Boris:
     'This pull request contains only one notable change:
       - Addition of the MTK NAND controller driver

      And a bunch of specific NAND driver improvements/fixes. Here are the
      changes that are worth mentioning:
       - A few fixes/improvements for the xway NAND controller driver
       - A few fixes for the sunxi NAND controller driver
       - Support for DMA in the sunxi NAND driver
       - Support for the sunxi NAND controller IP embedded in A23/A33 SoCs
       - Addition for bitflips detection in erased pages to the brcmnand driver
       - Support for new brcmnand IPs
       - Update of the OMAP-GPMC binding to support DMA channel description'

    In addition, some small fixes around error handling, etc., as well
    as one long-standing corner case issue (2.6.20, I think?) with
    writing 1 byte less than a page.

  NOR:

   - rework some error handling on reads and writes, so we can better
     handle (for instance) SPI controllers which have limitations on
     their maximum transfer size

   - add new Cadence Quad SPI flash controller driver

   - add new Atmel QSPI flash controller driver

   - add new Hisilicon SPI flash controller driver

   - support a few new flash, and update supported features on others

   - fix the logic used for detecting a fully-unlocked flash

  And other miscellaneous small fixes"

* tag 'for-linus-20160801' of git://git.infradead.org/linux-mtd: (60 commits)
  mtd: spi-nor: don't build Cadence QuadSPI on non-ARM
  mtd: mtk-nor: remove duplicated include from mtk-quadspi.c
  mtd: nand: fix bug writing 1 byte less than page size
  mtd: update description of MTD_BCM47XXSFLASH symbol
  mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller
  mtd: spi-nor: Bindings for Cadence Quad SPI Flash Controller driver
  mtd: nand: brcmnand: Change BUG_ON in brcmnand_send_cmd
  mtd: pmcmsp-flash: Allocating too much in init_msp_flash()
  mtd: maps: sa1100-flash: potential NULL dereference
  mtd: atmel-quadspi: add driver for Atmel QSPI controller
  mtd: nand: omap2: fix return value check in omap_nand_probe()
  Documentation: atmel-quadspi: add binding file for Atmel QSPI driver
  mtd: spi-nor: add hisilicon spi-nor flash controller driver
  mtd: spi-nor: support dual, quad, and WP for Gigadevice
  mtd: spi-nor: Added support for n25q00a.
  memory: Update dependency of IFC for Layerscape
  mtd: nand: jz4780: Update MODULE_AUTHOR email address
  mtd: nand: sunxi: prevent a small memory leak
  mtd: nand: sunxi: add reset line support
  mtd: nand: sunxi: update DT bindings
  ...
parents 44cee85a 1dcff2e4

Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt

+6 −1
Original line number Diff line number Diff line
@@ -46,6 +46,10 @@ Required properties: 
			0 maps to GPMC_WAIT0 pin.

 - gpio-cells:		Must be set to 2



Required properties when using NAND prefetch dma:

 - dmas			GPMC NAND prefetch dma channel

 - dma-names		Must be set to "rxtx"



Timing properties for child nodes. All are optional and default to 0.



 - gpmc,sync-clk-ps:	Minimum clock period for synchronous mode, in picoseconds
@@ -137,7 +141,8 @@ Example for an AM33xx board: 
		ti,hwmods = "gpmc";

		reg = <0x50000000 0x2000>;

		interrupts = <100>;



		dmas = <&edma 52 0>;

		dma-names = "rxtx";

		gpmc,num-cs = <8>;

		gpmc,num-waitpins = <2>;

		#address-cells = <2>;

Documentation/devicetree/bindings/mtd/atmel-quadspi.txt

0 → 100644
+32 −0
Original line number Diff line number Diff line 
* Atmel Quad Serial Peripheral Interface (QSPI)



Required properties:

- compatible:     Should be "atmel,sama5d2-qspi".

- reg:            Should contain the locations and lengths of the base registers

                  and the mapped memory.

- reg-names:      Should contain the resource reg names:

                  - qspi_base: configuration register address space

                  - qspi_mmap: memory mapped address space

- interrupts:     Should contain the interrupt for the device.

- clocks:         The phandle of the clock needed by the QSPI controller.

- #address-cells: Should be <1>.

- #size-cells:    Should be <0>.



Example:



spi@f0020000 {

	compatible = "atmel,sama5d2-qspi";

	reg = <0xf0020000 0x100>, <0xd0000000 0x8000000>;

	reg-names = "qspi_base", "qspi_mmap";

	interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;

	clocks = <&spi0_clk>;

	#address-cells = <1>;

	#size-cells = <0>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_spi0_default>;

	status = "okay";



	m25p80@0 {

		...

	};

};

Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt

+1 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ Required properties: 
                         brcm,brcmnand-v6.2

                         brcm,brcmnand-v7.0

                         brcm,brcmnand-v7.1

                         brcm,brcmnand-v7.2

                         brcm,brcmnand

- reg              : the register start and length for NAND register region.

                     (optional) Flash DMA register range (if present)

Documentation/devicetree/bindings/mtd/cadence-quadspi.txt

0 → 100644
+56 −0
Original line number Diff line number Diff line 
* Cadence Quad SPI controller



Required properties:

- compatible : Should be "cdns,qspi-nor".

- reg : Contains two entries, each of which is a tuple consisting of a

	physical address and length. The first entry is the address and

	length of the controller register set. The second entry is the

	address and length of the QSPI Controller data area.

- interrupts : Unit interrupt specifier for the controller interrupt.

- clocks : phandle to the Quad SPI clock.

- cdns,fifo-depth : Size of the data FIFO in words.

- cdns,fifo-width : Bus width of the data FIFO in bytes.

- cdns,trigger-address : 32-bit indirect AHB trigger address.



Optional properties:

- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.



Optional subnodes:

Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional

custom properties:

- cdns,read-delay : Delay for read capture logic, in clock cycles

- cdns,tshsl-ns : Delay in nanoseconds for the length that the master

                  mode chip select outputs are de-asserted between

		  transactions.

- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being

                  de-activated and the activation of another.

- cdns,tchsh-ns : Delay in nanoseconds between last bit of current

                  transaction and deasserting the device chip select

		  (qspi_n_ss_out).

- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low

                  and first bit transfer.



Example:



	qspi: spi@ff705000 {

		compatible = "cdns,qspi-nor";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0xff705000 0x1000>,

		      <0xffa00000 0x1000>;

		interrupts = <0 151 4>;

		clocks = <&qspi_clk>;

		cdns,is-decoded-cs;

		cdns,fifo-depth = <128>;

		cdns,fifo-width = <4>;

		cdns,trigger-address = <0x00000000>;



		flash0: n25q00@0 {

			...

			cdns,read-delay = <4>;

			cdns,tshsl-ns = <50>;

			cdns,tsd2d-ns = <50>;

			cdns,tchsh-ns = <4>;

			cdns,tslch-ns = <4>;

		};

	};

Documentation/devicetree/bindings/mtd/gpmc-nand.txt

+1 −1
Original line number Diff line number Diff line
@@ -39,7 +39,7 @@ Optional properties: 


		"prefetch-polled"	Prefetch polled mode (default)

		"polled"		Polled mode, without prefetch

		"prefetch-dma"		Prefetch enabled sDMA mode

		"prefetch-dma"		Prefetch enabled DMA mode

		"prefetch-irq"		Prefetch enabled irq mode



 - elm_id:	<deprecated> use "ti,elm-id" instead