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Commit afe2fcf5 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: convert CPU M/N timings to transcoder 



Same thing as the previous commits. Not renaming this one since it
exists since way before Haswell.

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent c9809791

drivers/gpu/drm/i915/i915_reg.h

+8 −8
Original line number Original line Diff line number Diff line
@@ -3305,14 +3305,14 @@ 
#define _PIPEB_LINK_M2           0x61048

#define _PIPEB_LINK_M2           0x61048

#define _PIPEB_LINK_N2           0x6104c

#define _PIPEB_LINK_N2           0x6104c





#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)

#define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)

#define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)

#define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)

#define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)

#define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2)

#define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)

#define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2)

#define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)

#define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1)

#define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)

#define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1)

#define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)

#define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2)

#define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)

#define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2)





/* CPU panel fitter */

/* CPU panel fitter */

/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */

/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */

drivers/gpu/drm/i915/intel_display.c

+5 −5
Original line number Original line Diff line number Diff line
@@ -4995,7 +4995,7 @@ static void ironlake_set_m_n(struct drm_crtc *crtc, 
	struct drm_device *dev = crtc->dev;

	struct drm_device *dev = crtc->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	enum pipe pipe = intel_crtc->pipe;

	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;

	struct intel_encoder *intel_encoder, *edp_encoder = NULL;

	struct intel_encoder *intel_encoder, *edp_encoder = NULL;

	struct fdi_m_n m_n = {0};

	struct fdi_m_n m_n = {0};

	int target_clock, pixel_multiplier, lane, link_bw;

	int target_clock, pixel_multiplier, lane, link_bw;
@@ -5058,10 +5058,10 @@ static void ironlake_set_m_n(struct drm_crtc *crtc, 
	ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,

	ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,

			     &m_n);

			     &m_n);





	I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);

	I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);

	I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);

	I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);

	I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);

	I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);

	I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);

	I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);

}

}





static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,

static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,

drivers/gpu/drm/i915/intel_dp.c

+6 −4
Original line number Original line Diff line number Diff line
@@ -777,6 +777,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 
	int lane_count = 4;

	int lane_count = 4;

	struct intel_dp_m_n m_n;

	struct intel_dp_m_n m_n;

	int pipe = intel_crtc->pipe;

	int pipe = intel_crtc->pipe;

	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;





	/*

	/*

	 * Find the lane count in the intel_encoder private

	 * Find the lane count in the intel_encoder private
@@ -801,10 +802,11 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 
			     mode->clock, adjusted_mode->clock, &m_n);

			     mode->clock, adjusted_mode->clock, &m_n);





	if (IS_HASWELL(dev)) {

	if (IS_HASWELL(dev)) {

		I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);

		I915_WRITE(PIPE_DATA_M1(cpu_transcoder),

		I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);

			   TU_SIZE(m_n.tu) | m_n.gmch_m);

		I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);

		I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);

		I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);

		I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);

		I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);

	} else if (HAS_PCH_SPLIT(dev)) {

	} else if (HAS_PCH_SPLIT(dev)) {

		I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);

		I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);

		I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);

		I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);