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Commit af951761 authored by ludovic.desroches@atmel.com's avatar ludovic.desroches@atmel.com Committed by Ulf Hansson
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mmc: sdhci: add quirk SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST 



The Atmel sdhci device needs a new quirk. sdhci_set_clock set the Clock
Control Register to 0 before computing the new value and writing it.
It disables the internal clock which causes a reset mecanism. If we
write the new value before this reset mecanism is done, it will prevent
the stabilisation of the internal clock, so a delay is needed. This
delay is about 2-3 cycles of the base clock. To be safe, a 1 ms delay is
used.

Signed-off-by: default avatarLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 2162d9f4

drivers/mmc/host/sdhci.c

+2 −0
Original line number Diff line number Diff line
@@ -1160,6 +1160,8 @@ void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 
	host->mmc->actual_clock = 0;



	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);

	if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)

		mdelay(1);



	if (clock == 0)

		return;

drivers/mmc/host/sdhci.h

+5 −0
Original line number Diff line number Diff line
@@ -412,6 +412,11 @@ struct sdhci_host { 
#define SDHCI_QUIRK2_ACMD23_BROKEN			(1<<14)

/* Broken Clock divider zero in controller */

#define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN		(1<<15)

/*

 * When internal clock is disabled, a delay is needed before modifying the

 * SD clock frequency or enabling back the internal clock.

 */

#define SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST	(1<<16)



	int irq;		/* Device IRQ */

	void __iomem *ioaddr;	/* Mapped address */