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Commit af777ce4 authored by Paul Mundt's avatar Paul Mundt
Browse files

sh: clkfwk: module_clk -> peripheral_clk rename. 



For consistenct naming, and to allow us to fix up some confusion in the
SH-Mobile clock framework, amongst other places.

Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent fd5b1245

arch/sh/kernel/cpu/clock.c

+3 −3
Original line number Diff line number Diff line
@@ -50,8 +50,8 @@ static struct clk master_clk = { 
	.rate		= CONFIG_SH_PCLK_FREQ,

};



static struct clk module_clk = {

	.name		= "module_clk",

static struct clk peripheral_clk = {

	.name		= "peripheral_clk",

	.parent		= &master_clk,

	.flags		= CLK_ENABLE_ON_INIT,

};
@@ -73,7 +73,7 @@ static struct clk cpu_clk = { 
 */

static struct clk *onchip_clocks[] = {

	&master_clk,

	&module_clk,

	&peripheral_clk,

	&bus_clk,

	&cpu_clk,

};

arch/sh/kernel/cpu/sh2/setup-sh7619.c

+2 −2
Original line number Diff line number Diff line
@@ -115,7 +115,7 @@ static struct sh_timer_config cmt0_platform_data = { 
	.name = "CMT0",

	.channel_offset = 0x02,

	.timer_bit = 0,

	.clk = "module_clk",

	.clk = "peripheral_clk",

	.clockevent_rating = 125,

	.clocksource_rating = 0, /* disabled due to code generation issues */

};
@@ -147,7 +147,7 @@ static struct sh_timer_config cmt1_platform_data = { 
	.name = "CMT1",

	.channel_offset = 0x08,

	.timer_bit = 1,

	.clk = "module_clk",

	.clk = "peripheral_clk",

	.clockevent_rating = 125,

	.clocksource_rating = 0, /* disabled due to code generation issues */

};

arch/sh/kernel/cpu/sh2a/setup-mxg.c

+3 −3
Original line number Diff line number Diff line
@@ -118,7 +118,7 @@ static struct sh_timer_config mtu2_0_platform_data = { 
	.name = "MTU2_0",

	.channel_offset = -0x80,

	.timer_bit = 0,

	.clk = "module_clk",

	.clk = "peripheral_clk",

	.clockevent_rating = 200,

};
@@ -149,7 +149,7 @@ static struct sh_timer_config mtu2_1_platform_data = { 
	.name = "MTU2_1",

	.channel_offset = -0x100,

	.timer_bit = 1,

	.clk = "module_clk",

	.clk = "peripheral_clk",

	.clockevent_rating = 200,

};
@@ -180,7 +180,7 @@ static struct sh_timer_config mtu2_2_platform_data = { 
	.name = "MTU2_2",

	.channel_offset = 0x80,

	.timer_bit = 2,

	.clk = "module_clk",

	.clk = "peripheral_clk",

	.clockevent_rating = 200,

};

arch/sh/kernel/cpu/sh2a/setup-sh7201.c

+3 −3
Original line number Diff line number Diff line
@@ -255,7 +255,7 @@ static struct sh_timer_config mtu2_0_platform_data = { 
	.name = "MTU2_0",

	.channel_offset = -0x80,

	.timer_bit = 0,

	.clk = "module_clk",

	.clk = "peripheral_clk",

	.clockevent_rating = 200,

};
@@ -286,7 +286,7 @@ static struct sh_timer_config mtu2_1_platform_data = { 
	.name = "MTU2_1",

	.channel_offset = -0x100,

	.timer_bit = 1,

	.clk = "module_clk",

	.clk = "peripheral_clk",

	.clockevent_rating = 200,

};
@@ -317,7 +317,7 @@ static struct sh_timer_config mtu2_2_platform_data = { 
	.name = "MTU2_2",

	.channel_offset = 0x80,

	.timer_bit = 2,

	.clk = "module_clk",

	.clk = "peripheral_clk",

	.clockevent_rating = 200,

};

arch/sh/kernel/cpu/sh2a/setup-sh7203.c

+4 −4
Original line number Diff line number Diff line
@@ -211,7 +211,7 @@ static struct sh_timer_config cmt0_platform_data = { 
	.name = "CMT0",

	.channel_offset = 0x02,

	.timer_bit = 0,

	.clk = "module_clk",

	.clk = "peripheral_clk",

	.clockevent_rating = 125,

	.clocksource_rating = 0, /* disabled due to code generation issues */

};
@@ -243,7 +243,7 @@ static struct sh_timer_config cmt1_platform_data = { 
	.name = "CMT1",

	.channel_offset = 0x08,

	.timer_bit = 1,

	.clk = "module_clk",

	.clk = "peripheral_clk",

	.clockevent_rating = 125,

	.clocksource_rating = 0, /* disabled due to code generation issues */

};
@@ -275,7 +275,7 @@ static struct sh_timer_config mtu2_0_platform_data = { 
	.name = "MTU2_0",

	.channel_offset = -0x80,

	.timer_bit = 0,

	.clk = "module_clk",

	.clk = "peripheral_clk",

	.clockevent_rating = 200,

};
@@ -306,7 +306,7 @@ static struct sh_timer_config mtu2_1_platform_data = { 
	.name = "MTU2_1",

	.channel_offset = -0x100,

	.timer_bit = 1,

	.clk = "module_clk",

	.clk = "peripheral_clk",

	.clockevent_rating = 200,

};