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Commit ad882137 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

arm64: KVM: Add temporary kvm_perf_event.h 



In order to merge the KVM/ARM PMU patches without creating a
conflict mess, let's have a temporary include file that won't
conflict with anything. Subsequent patches will clean that up.

Acked-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent 21a4179c

arch/arm64/include/asm/kvm_host.h

+1 −0
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@@ -27,6 +27,7 @@ 
#include <asm/kvm.h>

#include <asm/kvm_asm.h>

#include <asm/kvm_mmio.h>

#include <asm/kvm_perf_event.h>



#define __KVM_HAVE_ARCH_INTC_INITIALIZED

arch/arm64/include/asm/kvm_perf_event.h

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+55 −0
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/*

 * Copyright (C) 2012 ARM Ltd.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */



#ifndef __ASM_KVM_PERF_EVENT_H

#define __ASM_KVM_PERF_EVENT_H



#define	ARMV8_PMU_MAX_COUNTERS	32

#define	ARMV8_PMU_COUNTER_MASK	(ARMV8_PMU_MAX_COUNTERS - 1)



/*

 * Per-CPU PMCR: config reg

 */

#define ARMV8_PMU_PMCR_E	(1 << 0) /* Enable all counters */

#define ARMV8_PMU_PMCR_P	(1 << 1) /* Reset all counters */

#define ARMV8_PMU_PMCR_C	(1 << 2) /* Cycle counter reset */

#define ARMV8_PMU_PMCR_D	(1 << 3) /* CCNT counts every 64th cpu cycle */

#define ARMV8_PMU_PMCR_X	(1 << 4) /* Export to ETM */

#define ARMV8_PMU_PMCR_DP	(1 << 5) /* Disable CCNT if non-invasive debug*/

#define	ARMV8_PMU_PMCR_N_SHIFT	11	 /* Number of counters supported */

#define	ARMV8_PMU_PMCR_N_MASK	0x1f

#define	ARMV8_PMU_PMCR_MASK	0x3f	 /* Mask for writable bits */



/*

 * PMOVSR: counters overflow flag status reg

 */

#define	ARMV8_PMU_OVSR_MASK		0xffffffff	/* Mask for writable bits */

#define	ARMV8_PMU_OVERFLOWED_MASK	ARMV8_PMU_OVSR_MASK



/*

 * PMXEVTYPER: Event selection reg

 */

#define	ARMV8_PMU_EVTYPE_MASK	0xc80003ff	/* Mask for writable bits */

#define	ARMV8_PMU_EVTYPE_EVENT	0x3ff		/* Mask for EVENT bits */



/*

 * Event filters for PMUv3

 */

#define	ARMV8_PMU_EXCLUDE_EL1	(1 << 31)

#define	ARMV8_PMU_EXCLUDE_EL0	(1 << 30)

#define	ARMV8_PMU_INCLUDE_EL2	(1 << 27)



#endif