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Commit ad67ef68 authored by Paul Walmsley's avatar Paul Walmsley Committed by Tony Lindgren
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ARM: OMAP2: Powerdomain: Add base OMAP2/3 powerdomain code 



This patch creates an interface to the powerdomain registers in the
PRM/CM modules on OMAP2/3.  This interface is intended to be used by
PM code, e.g., pm.c; not by device drivers directly.

Each powerdomain will be defined in later patches as static
structures.  Also defined are dependencies between powerdomains,
used for adding and removing PM_WKDEP and CM_SLEEPDEP bits.  The
powerdomain structures are linked into a list at boot by
pwrdm_register(), similar to the OMAP clock code.

The patch adds a Kconfig option, CONFIG_OMAP_DEBUG_POWERDOMAIN, which
when enabled will emit verbose debug messages via pr_debug().

Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 1fca2542

arch/arm/mach-omap2/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ 


# Common support

obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \

		devices.o serial.o gpmc.o timer-gp.o

		devices.o serial.o gpmc.o timer-gp.o powerdomain.o



obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o

arch/arm/mach-omap2/clock34xx.c

+17 −10
Original line number Diff line number Diff line
@@ -62,11 +62,14 @@ static void omap3_dpll_recalc(struct clk *clk) 
static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)

{

	const struct dpll_data *dd;

	u32 v;



	dd = clk->dpll_data;



	cm_rmw_reg_bits(dd->enable_mask, clken_bits << __ffs(dd->enable_mask),

			dd->control_reg);

	v = __raw_readl(dd->control_reg);

	v &= ~dd->enable_mask;

	v |= clken_bits << __ffs(dd->enable_mask);

	__raw_writel(v, dd->control_reg);

}



/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
@@ -82,7 +85,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) 
	state <<= dd->idlest_bit;

	idlest_mask = 1 << dd->idlest_bit;



	while (((cm_read_reg(dd->idlest_reg) & idlest_mask) != state) &&

	while (((__raw_readl(dd->idlest_reg) & idlest_mask) != state) &&

	       i < MAX_DPLL_WAIT_TRIES) {

		i++;

		udelay(1);
@@ -285,7 +288,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk) 


	dd = clk->dpll_data;



	v = cm_read_reg(dd->autoidle_reg);

	v = __raw_readl(dd->autoidle_reg);

	v &= dd->autoidle_mask;

	v >>= __ffs(dd->autoidle_mask);
@@ -304,6 +307,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk) 
static void omap3_dpll_allow_idle(struct clk *clk)

{

	const struct dpll_data *dd;

	u32 v;



	if (!clk || !clk->dpll_data)

		return;
@@ -315,9 +319,10 @@ static void omap3_dpll_allow_idle(struct clk *clk) 
	 * by writing 0x5 instead of 0x1.  Add some mechanism to

	 * optionally enter this mode.

	 */

	cm_rmw_reg_bits(dd->autoidle_mask,

			DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask),

			dd->autoidle_reg);

	v = __raw_readl(dd->autoidle_reg);

	v &= ~dd->autoidle_mask;

	v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);

	__raw_writel(v, dd->autoidle_reg);

}



/**
@@ -329,15 +334,17 @@ static void omap3_dpll_allow_idle(struct clk *clk) 
static void omap3_dpll_deny_idle(struct clk *clk)

{

	const struct dpll_data *dd;

	u32 v;



	if (!clk || !clk->dpll_data)

		return;



	dd = clk->dpll_data;



	cm_rmw_reg_bits(dd->autoidle_mask,

			DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask),

			dd->autoidle_reg);

	v = __raw_readl(dd->autoidle_reg);

	v &= ~dd->autoidle_mask;

	v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);

	__raw_writel(v, dd->autoidle_reg);

}



/* Clock control for DPLL outputs */