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Commit aae95ca7 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/fb: implement various bits of work towards memory reclocking 



Not even remotely ready for the vast majority of the world.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 26fdd78c

drivers/gpu/drm/nouveau/Makefile

+4 −0
Original line number Diff line number Diff line
@@ -94,6 +94,7 @@ nouveau-y += core/subdev/fb/nva3.o 
nouveau-y += core/subdev/fb/nvaa.o

nouveau-y += core/subdev/fb/nvaf.o

nouveau-y += core/subdev/fb/nvc0.o

nouveau-y += core/subdev/fb/nve0.o

nouveau-y += core/subdev/fb/ramnv04.o

nouveau-y += core/subdev/fb/ramnv10.o

nouveau-y += core/subdev/fb/ramnv1a.o
@@ -107,6 +108,9 @@ nouveau-y += core/subdev/fb/ramnv50.o 
nouveau-y += core/subdev/fb/ramnva3.o

nouveau-y += core/subdev/fb/ramnvaa.o

nouveau-y += core/subdev/fb/ramnvc0.o

nouveau-y += core/subdev/fb/ramnve0.o

nouveau-y += core/subdev/fb/sddr3.o

nouveau-y += core/subdev/fb/gddr5.o

nouveau-y += core/subdev/gpio/base.o

nouveau-y += core/subdev/gpio/nv10.o

nouveau-y += core/subdev/gpio/nv50.o

drivers/gpu/drm/nouveau/core/engine/device/nve0.c

+5 −5
Original line number Diff line number Diff line
@@ -69,7 +69,7 @@ nve0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;

		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_FB     ] =  nvc0_fb_oclass;

		device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;

		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;

		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
@@ -102,7 +102,7 @@ nve0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;

		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_FB     ] =  nvc0_fb_oclass;

		device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;

		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;

		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
@@ -135,7 +135,7 @@ nve0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;

		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_FB     ] =  nvc0_fb_oclass;

		device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;

		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;

		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
@@ -168,7 +168,7 @@ nve0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;

		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_FB     ] =  nvc0_fb_oclass;

		device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;

		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;

		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
@@ -203,7 +203,7 @@ nve0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;

		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_FB     ] =  nvc0_fb_oclass;

		device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;

		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;

		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;

drivers/gpu/drm/nouveau/core/include/subdev/fb.h

+9 −0
Original line number Diff line number Diff line
@@ -99,6 +99,7 @@ extern struct nouveau_oclass *nva3_fb_oclass; 
extern struct nouveau_oclass *nvaa_fb_oclass;

extern struct nouveau_oclass *nvaf_fb_oclass;

extern struct nouveau_oclass *nvc0_fb_oclass;

extern struct nouveau_oclass *nve0_fb_oclass;



struct nouveau_ram {

	struct nouveau_object base;
@@ -125,9 +126,17 @@ struct nouveau_ram { 
	int  (*get)(struct nouveau_fb *, u64 size, u32 align,

		    u32 size_nc, u32 type, struct nouveau_mem **);

	void (*put)(struct nouveau_fb *, struct nouveau_mem **);



	int  (*calc)(struct nouveau_fb *, u32 freq);

	int  (*prog)(struct nouveau_fb *);

	void (*tidy)(struct nouveau_fb *);

	struct {

		u8  version;

		u32 data;

		u8  size;

	} rammap, ramcfg, timing;

	u32 freq;

	u32 mr[16];

};



#endif

drivers/gpu/drm/nouveau/core/subdev/clock/pllnva3.c

+1 −0
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ nva3_pll_calc(struct nouveau_subdev *subdev, struct nvbios_pll *info, 
	lM = max(lM, (int)info->vco1.min_m);

	hM = (info->refclk + info->vco1.min_inputfreq) / info->vco1.min_inputfreq;

	hM = min(hM, (int)info->vco1.max_m);

	lM = min(lM, hM);



	for (M = lM; M <= hM; M++) {

		u32 tmp = freq * *P * M;

drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c

0 → 100644
+96 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2013 Red Hat Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Ben Skeggs <bskeggs@redhat.com>

 */



#include <subdev/bios.h>

#include "priv.h"



int

nouveau_gddr5_calc(struct nouveau_ram *ram)

{

	struct nouveau_bios *bios = nouveau_bios(ram);

	int pd, lf, xd, vh, vr, vo;

	int WL, CL, WR, at, dt, ds;

	int rq = ram->freq < 1000000; /* XXX */



	switch (!!ram->ramcfg.data * ram->ramcfg.version) {

	case 0x11:

		pd =  (nv_ro08(bios, ram->ramcfg.data + 0x01) & 0x80) >> 7;

		lf =  (nv_ro08(bios, ram->ramcfg.data + 0x01) & 0x40) >> 6;

		xd = !(nv_ro08(bios, ram->ramcfg.data + 0x01) & 0x20);

		vh =  (nv_ro08(bios, ram->ramcfg.data + 0x02) & 0x10) >> 4;

		vr =  (nv_ro08(bios, ram->ramcfg.data + 0x02) & 0x04) >> 2;

		vo =   nv_ro08(bios, ram->ramcfg.data + 0x06) & 0xff;

		break;

	default:

		return -ENOSYS;

	}



	switch (!!ram->timing.data * ram->timing.version) {

	case 0x20:

		WL = (nv_ro16(bios, ram->timing.data + 0x04) & 0x0f80) >> 7;

		CL =  nv_ro08(bios, ram->timing.data + 0x04) & 0x1f;

		WR =  nv_ro08(bios, ram->timing.data + 0x0a) & 0x7f;

		at = (nv_ro08(bios, ram->timing.data + 0x2e) & 0xc0) >> 6;

		dt =  nv_ro08(bios, ram->timing.data + 0x2e) & 0x03;

		ds =  nv_ro08(bios, ram->timing.data + 0x2f) & 0x03;

		break;

	default:

		return -ENOSYS;

	}



	if (WL < 1 || WL > 7 || CL < 5 || CL > 36 || WR < 4 || WR > 35)

		return -EINVAL;

	CL -= 5;

	WR -= 4;



	ram->mr[0] &= ~0xf7f;

	ram->mr[0] |= (WR & 0x0f) << 8;

	ram->mr[0] |= (CL & 0x0f) << 3;

	ram->mr[0] |= (WL & 0x07) << 0;



	ram->mr[1] &= ~0x0bf;

	ram->mr[1] |= (xd & 0x01) << 7;

	ram->mr[1] |= (at & 0x03) << 4;

	ram->mr[1] |= (dt & 0x03) << 2;

	ram->mr[1] |= (ds & 0x03) << 0;



	ram->mr[3] &= ~0x020;

	ram->mr[3] |= (rq & 0x01) << 5;



	if (!vo)

		vo = (ram->mr[6] & 0xff0) >> 4;

	if (ram->mr[6] & 0x001)

		pd = 1; /* binary driver does this.. bug? */

	ram->mr[6] &= ~0xff1;

	ram->mr[6] |= (vo & 0xff) << 4;

	ram->mr[6] |= (pd & 0x01) << 0;



	if (!(ram->mr[7] & 0x100))

		vr = 0; /* binary driver does this.. bug? */

	ram->mr[7] &= ~0x188;

	ram->mr[7] |= (vr & 0x01) << 8;

	ram->mr[7] |= (vh & 0x01) << 7;

	ram->mr[7] |= (lf & 0x01) << 3;

	return 0;

}